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M36L0R8060L3ZAMF PDF预览

M36L0R8060L3ZAMF

更新时间： 2024-11-19 04:50:59
品牌 Logo 应用领域
恒忆 - NUMONYX 内存集成电路
页数 文件大小 规格书
29页 559K
描述
Memory Circuit, 16MX16, CMOS, PBGA88, 8 X 10 MM, 0.80 MM PITCH, ROHS COMPLIANT, TFBGA-88

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M36L0R8060L3ZAMF 数据手册

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M36L0Rx0x0UL3  
128- or 256-Mbit (mux I/O, multiple bank, multilevel, burst) flash  
memory, and 32- or 64-Mbit PSRAM, 1.8 V supply MCP  
Target Specification  
Features  
■ Multichip package  
FBGA  
– 1 die of 128 Mbits (8 Mbits x16) or 256  
Mbits (16 Mbits x16), mux I/O multiple  
bank, multilevel, burst flash memory  
– 1 die of 32 or 64 Mbits mux I/O, burst  
PSRAM  
TFBGA56 (ZS)  
8 x 6 mm  
TFBGA88 (ZAM)  
8 x 10 mm  
■ Supply voltage  
– V  
– V  
= V  
= V = 1.7 to 1.95 V  
DDQF  
■ Security  
DDF  
PPF  
DDP  
= 9 V for fast program  
– 64-bit unique device number  
– 2112-bit user programmable OTP cells  
■ Electronic signature  
– Manufacturer code: 20h  
■ Common flash interface (CFI)  
– Device codes (top flash configuration):  
M36L0R7050U3/M36L0R7060U3: 882Eh  
M36L0R8050U3/M36L0R8060U3: 881Ch  
■ 100,000 program/erase cycles per block  
PSRAM  
■ Access time: 70 ns  
– Device codes (bottom flash configuration)  
M36L0R7050L3/M36L0R7060L3: 882Fh  
M36L0R8050L3/M36L0R8060L3: 881Dh  
■ Synchronous modes:  
– Synchronous write: continuous burst  
Flash memory  
– Synchronous read: continuous burst or  
fixed length: 4, 8 or 16 words for 32-Mbit  
devices; 4, 8, 16 or 32 words for 64-Mbit  
devices  
■ Synchronous/asynchronous read  
– Synchronous burst read mode: 66 MHz  
– Random access: 70 ns  
– Maximum clock frequency: 83 MHz  
■ Programming time  
■ Low-power features  
– 2.5 µs typical word program time using  
buffer enhanced factory program command  
– Partial array self-refresh (PASR)  
– Deep power-down (DPD) mode  
■ Memory organization  
– Automatic temperature-compensated self-  
refresh  
– Multiple bank memory array: 8-Mbit banks  
– Parameter blocks (top or bottom location)  
Table 1.  
Device summary  
M36L0Rx0xoUL3  
■ Dual operations  
– Program/erase in one bank, read in others  
■ Block locking  
M36L0R7050U3  
M36L0R7060U3  
M36L0R8050U3  
M36L0R8060U3  
M36L0R7050L3  
M36L0R7060L3  
M36L0R8050L3  
M36L0R8060L3  
– All blocks locked at power-up  
– Any combination of blocks can be locked  
with zero latency  
– WP for block lock-down  
F
– Absolute write protection with V  
= V  
SS  
PPF  
March 2008  
Rev 2  
1/29  
This is preliminary information on a new product foreseen to be developed. Details are subject to change without notice.  
www.numonyx.com  
1
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 		256 Mbit (Multiple Bank, Multi-Level, Burst) Flash Memory and 64 Mbit (Burst) PSRAM, 1.8V
M36L0R8060T1ZAQF STMICROELECTRONICS

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 		256 Mbit (Multiple Bank, Multi-Level, Burst) Flash Memory and 64 Mbit (Burst) PSRAM, 1.8V
M36L0R8060T1ZAQT STMICROELECTRONICS

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 		256 Mbit (Multiple Bank, Multi-Level, Burst) Flash Memory and 64 Mbit (Burst) PSRAM, 1.8V
M36L0R8060U3ZAME NUMONYX

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 		Memory Circuit, 16MX16, CMOS, PBGA88, 8 X 10 MM, 0.80 MM PITCH, ROHS COMPLIANT, TFBGA-88

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