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M36L0T7050B0ZAQT PDF预览

M36L0T7050B0ZAQT

更新时间： 2024-02-19 13:04:13
品牌 Logo 应用领域
恒忆 - NUMONYX 静态存储器内存集成电路
页数 文件大小 规格书
18页 361K
描述
Memory Circuit, 8MX16, CMOS, PBGA88, 8 X 10 MM, 0.80 MM PITCH, TFBGA-88

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中文翻译

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M36L0T7050B0ZAQT 技术参数

生命周期：Transferred零件包装代码：BGA
包装说明：TFBGA,针数：88
Reach Compliance Code：unknownHTS代码：8542.32.00.71
风险等级：5.1其他特性：PSRAM IS ORGANIZED AS 2M X 16
JESD-30 代码：R-PBGA-B88JESD-609代码：e0
长度：10 mm内存密度：134217728 bit
内存集成电路类型：MEMORY CIRCUIT内存宽度：16
功能数量：1端子数量：88
字数：8388608 words字数代码：8000000
工作模式：ASYNCHRONOUS最高工作温度：85 °C
最低工作温度：-25 °C组织：8MX16
封装主体材料：PLASTIC/EPOXY封装代码：TFBGA
封装形状：RECTANGULAR封装形式：GRID ARRAY, THIN PROFILE, FINE PITCH
峰值回流温度（摄氏度）：NOT SPECIFIED认证状态：Not Qualified
座面最大高度：1.2 mm最大供电电压 (Vsup)：1.95 V
最小供电电压 (Vsup)：1.7 V表面贴装：YES
技术：CMOS温度等级：OTHER
端子面层：TIN LEAD端子形式：BALL
端子节距：0.8 mm端子位置：BOTTOM
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：8 mm
Base Number Matches：1

M36L0T7050B0ZAQT 数据手册

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M36L0T7050T0  
M36L0T7050B0  
128Mbit (Multiple Bank, Multi-Level, Burst) Flash Memory  
32Mbit (2M x16) PSRAM, Multi-Chip Package  
FEATURES SUMMARY  
■
MULTI-CHIP PACKAGE  
Figure 1. Package  
–
1 die of 128Mbit (8Mx16, Multiple Bank,  
Multi-level, Burst) Flash Memory  
–
1 die of 32Mbit (2Mx16) Pseudo SRAM  
■
SUPPLY VOLTAGE  
–
–
–
VDDF = 1.7 to 2V  
VDDP = VDDQ = 2.7 to 3.3V  
FBGA  
VPP = 9V for fast program (12V tolerant)  
■
■
ELECTRONIC SIGNATURE  
–
–
Manufacturer Code: 20h  
Device Code (Top Flash Configuration)  
M36L0T7050T0: 88C4h  
TFBGA88 (ZAQ)  
8 x 10mm  
–
Device Code (Bottom Flash  
Configuration) M36L0T7050B0: 88C5h  
PACKAGE  
–
Compliant with Lead-Free Soldering  
Processes  
■
BLOCK LOCKING  
–
–
All blocks locked at power-up  
Any combination of blocks can be locked  
with zero latency  
WP for Block Lock-Down  
Absolute Write Protection with VPP = VSS  
–
Lead-Free Versions  
FLASH MEMORY  
■
SYNCHRONOUS / ASYNCHRONOUS READ  
–
–
–
–
–
Synchronous Burst Read mode: 50MHz  
Asynchronous Page Read mode  
Random Access: 90ns  
■
■
COMMON FLASH INTERFACE (CFI)  
100,000 PROGRAM/ERASE CYCLES per  
BLOCK  
■
■
SYNCHRONOUS BURST READ SUSPEND  
PROGRAMMING TIME  
–
PSRAM  
10µs typical Word program time using  
Write to Buffer and Program  
■
■
■
■
■
■
■
ACCESS TIME: 70ns  
LOW STANDBY CURRENT: 100µA  
DEEP POWER-DOWN CURRENT: 10µA  
BYTE CONTROL: UBP/LBP  
PROGRAMMABLE PARTIAL ARRAY  
8 WORD PAGE ACCESS CAPABILITY: 18ns  
POWER-DOWN MODES  
■
■
■
MEMORY ORGANIZATION  
–
Multiple Bank Memory Array: 8 Mbit  
Banks  
Parameter Blocks (Top or Bottom  
location)  
–
DUAL OPERATIONS  
–
program/erase in one Bank while read in  
others  
No delay between read and write  
operations  
– Deep Power-Down  
– 4 Mbit Partial Array Refresh  
– 8 Mbit Partial Array Refresh  
– 16 Mbit Partial Array Refresh  
–
SECURITY  
–
–
64 bit unique device number  
2112 bit user programmable OTP Cells  
December 2004  
1/18  
1234567...18

中文翻译

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与M36L0T7050B0ZAQT相关器件

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M36L0T7050B2 NUMONYX

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 		128 Mbit (Multiple Bank, Multi-Level, Burst) Flash memory and 32 Mbit (2Mb x16) PSRAM, Mul
M36L0T7050B2ZAQ NUMONYX

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 		128 Mbit (Multiple Bank, Multi-Level, Burst) Flash memory and 32 Mbit (2Mb x16) PSRAM, Mul
M36L0T7050B2ZAQE NUMONYX

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 		128 Mbit (Multiple Bank, Multi-Level, Burst) Flash memory and 32 Mbit (2Mb x16) PSRAM, Mul
M36L0T7050B2ZAQF NUMONYX

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 		128 Mbit (Multiple Bank, Multi-Level, Burst) Flash memory and 32 Mbit (2Mb x16) PSRAM, Mul
M36L0T7050B2ZAQT NUMONYX

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 		128 Mbit (Multiple Bank, Multi-Level, Burst) Flash memory and 32 Mbit (2Mb x16) PSRAM, Mul
M36L0T7050T0 STMICROELECTRONICS

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 		128Mbit (Multiple Bank, Multi-Level, Burst) Flash Memory 32Mbit (2M x16) PSRAM, Multi-Chip
M36L0T7050T0ZAQ NUMONYX

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 		Memory Circuit, 8MX16, CMOS, PBGA88, 8 X 10 MM, 0.80 MM PITCH, TFBGA-88
M36L0T7050T0ZAQE STMICROELECTRONICS

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 		128Mbit (Multiple Bank, Multi-Level, Burst) Flash Memory 32Mbit (2M x16) PSRAM, Multi-Chip
M36L0T7050T0ZAQF STMICROELECTRONICS

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 		128Mbit (Multiple Bank, Multi-Level, Burst) Flash Memory 32Mbit (2M x16) PSRAM, Multi-Chip
M36L0T7050T0ZAQF NUMONYX

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 		Memory Circuit, 8MX16, CMOS, PBGA88, 8 X 10 MM, 0.80 MM PITCH, LEAD FREE, TFBGA-88

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