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M36L0T7050 PDF预览

M36L0T7050

更新时间: 2024-11-17 21:54:39
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 闪存静态存储器
页数 文件大小 规格书
18页 409K
描述
128 Mbit (Multiple Bank, Multi-Level, Burst) Flash Memory 32 Mbit (2M x16) PSRAM, 1.8V Supply Multi-Chip Package

M36L0T7050 数据手册

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M36L0R7050T0  
M36L0R7050B0  
128 Mbit (Multiple Bank, Multi-Level, Burst) Flash Memory  
32 Mbit (2M x16) PSRAM, 1.8V Supply Multi-Chip Package  
FEATURES SUMMARY  
MULTI-CHIP PACKAGE  
Figure 1. Package  
1 die of 128 Mbit (8Mb x16, Multiple Bank,  
Multi-level, Burst) Flash Memory  
1 die of 32 Mbit (2Mb x16) Asynchronous  
Pseudo SRAM  
SUPPLY VOLTAGE  
FBGA  
VDDF = VDDP = VDDQ = 1.7 to 1.95V  
VPPF = 9V for fast program (12V tolerant)  
ELECTRONIC SIGNATURE  
Manufacturer Code: 20h  
Device Code (Top Flash Configuration)  
M36L0R7050T0: 88C4h  
TFBGA88 (ZAQ)  
8 x 10mm  
Device Code (Bottom Flash  
Configuration) M36L0R7050B0: 88C5h  
PACKAGE  
Compliant with Lead-Free Soldering  
Processes  
Lead-Free Versions  
BLOCK LOCKING  
FLASH MEMORY  
All blocks locked at power-up  
Any combination of blocks can be locked  
with zero latency  
WPF for Block Lock-Down  
Absolute Write Protection with VPPF = VSS  
SYNCHRONOUS / ASYNCHRONOUS READ  
Synchronous Burst Read mode: 54MHz  
Asynchronous Page Read mode  
Random Access: 85ns  
SYNCHRONOUS BURST READ SUSPEND  
PROGRAMMING TIME  
COMMON FLASH INTERFACE (CFI)  
100,000 PROGRAM/ERASE CYCLES per  
BLOCK  
10µs typical Word program time using  
Buffer Program  
PSRAM  
MEMORY ORGANIZATION  
ACCESS TIME: 85ns  
Multiple Bank Memory Array: 8 Mbit  
Banks  
LOW STANDBY CURRENT: 100µA  
DEEP POWER-DOWN CURRENT: 10µA  
BYTE CONTROL: UBP/LBP  
PROGRAMMABLE PARTIAL ARRAY  
8 WORD PAGE ACCESS CAPABILITY: 25ns  
PARTIAL POWER-DOWN MODES  
Parameter Blocks (Top or Bottom  
location)  
DUAL OPERATIONS  
program/erase in one Bank while read in  
others  
No delay between read and write  
operations  
Deep Power-Down  
4 Mbit Partial Power-Down  
8 Mbit Partial Power-Down  
16 Mbit Partial Power-Down  
SECURITY  
64 bit unique device number  
2112 bit user programmable OTP Cells  
December 2004  
1/18  

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