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M36L0T7050B2ZAQF PDF预览

M36L0T7050B2ZAQF

更新时间: 2024-11-18 02:52:43
品牌 Logo 应用领域
恒忆 - NUMONYX 闪存存储内存集成电路静态存储器
页数 文件大小 规格书
22页 443K
描述
128 Mbit (Multiple Bank, Multi-Level, Burst) Flash memory and 32 Mbit (2Mb x16) PSRAM, Multi-Chip Package

M36L0T7050B2ZAQF 技术参数

是否Rohs认证:符合生命周期:Transferred
零件包装代码:BGA包装说明:TFBGA, BGA88,8X12,32
针数:88Reach Compliance Code:unknown
HTS代码:8542.32.00.71风险等级:5.08
Is Samacsys:N最长访问时间:85 ns
其他特性:PSRAM IS ORGANIZED AS 2M X 16JESD-30 代码:R-PBGA-B88
长度:10 mm内存密度:134217728 bit
内存集成电路类型:MEMORY CIRCUIT内存宽度:16
混合内存类型:FLASH+PSRAM功能数量:1
端子数量:88字数:8388608 words
字数代码:8000000工作模式:SYNCHRONOUS
最高工作温度:85 °C最低工作温度:-25 °C
组织:8MX16封装主体材料:PLASTIC/EPOXY
封装代码:TFBGA封装等效代码:BGA88,8X12,32
封装形状:RECTANGULAR封装形式:GRID ARRAY, THIN PROFILE, FINE PITCH
峰值回流温度(摄氏度):NOT SPECIFIED电源:1.8,3 V
认证状态:Not Qualified座面最大高度:1.2 mm
最大待机电流:0.0001 A子类别:Other Memory ICs
最大供电电压 (Vsup):1.95 V最小供电电压 (Vsup):1.7 V
表面贴装:YES技术:CMOS
温度等级:OTHER端子形式:BALL
端子节距:0.8 mm端子位置:BOTTOM
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:8 mm
Base Number Matches:1

M36L0T7050B2ZAQF 数据手册

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M36L0T7050T2  
M36L0T7050B2  
128 Mbit (Multiple Bank, Multi-Level, Burst) Flash memory  
and 32 Mbit (2Mb x16) PSRAM, Multi-Chip Package  
Preliminary Data  
Feature summary  
Multi-Chip Package  
– 1 die of 128 Mbit (8Mb x16, Multiple Bank,  
Multi-level, Burst) Flash Memory  
FBGA  
– 1 die of 32 Mbit (2Mb x16) Pseudo SRAM  
Supply voltage  
– V  
– V  
– V  
= 1.7 to 1.95V  
DDF  
CCP  
PPF  
TFBGA88 (ZAQ)  
8 x 10mm  
= V  
= 2.7 to 3.1V  
DDQ  
= 9V for fast program  
Electronic signature  
Block locking  
– Manufacturer Code: 20h  
– All blocks locked at power-up  
– Device Code (Top Flash Configuration)  
M36L0T7050T2: 88C4h  
– Device Code (Bottom Flash Configuration)  
M36L0T7050B2: 88C5h  
– Any combination of blocks can be locked  
with zero latency  
– WP for Block Lock-Down  
– Absolute Write Protection with V = V  
ECOPACK® packages available  
PP  
SS  
Security  
– 64 bit unique device number  
Flash memory  
Synchronous / Asynchronous Read  
– Synchronous Burst Read mode: 52MHz  
– Random Access: 85ns  
– 2112 bit user programmable OTP Cells  
Common Flash Interface (CFI)  
100,000 program/erase cycles per block  
Synchronous Burst Read Suspend  
Programming time  
PSRAM  
– 2.5µs typical Word program time using  
Buffer Enhanced Factory Program  
command  
Access time: 65ns  
8-Word Page Access capability: 18ns  
Low standby current: 100µA  
Deep power down current: 10µA  
Compatible with standard LPSRAM  
Memory organization  
– Multiple Bank Memory Array: 8 Mbit Banks  
– Parameter Blocks (Top or Bottom location)  
Power-down modes  
Dual operations  
– Deep Power-Down  
– 4 Mbit Partial Array Refresh  
– 8 Mbit Partial Array Refresh  
– program/erase in one Bank while read in  
others  
– No delay between read and write  
operations  
November 2007  
Rev 0.2  
1/22  
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to  
change without notice.  
www.numonyx.com  
1

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