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K3N6U1000C-GC150 PDF预览

K3N6U1000C-GC150

更新时间: 2024-11-24 19:59:07
品牌 Logo 应用领域
三星 - SAMSUNG 有原始数据的样本ROM光电二极管内存集成电路
页数 文件大小 规格书
4页 72K
描述
MASK ROM, 2MX16, 150ns, CMOS, PDSO44, 0.600 INCH, SOP-44

K3N6U1000C-GC150 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:SOIC包装说明:SOP,
针数:44Reach Compliance Code:compliant
ECCN代码:EAR99HTS代码:8542.32.00.71
风险等级:5.92最长访问时间:150 ns
备用内存宽度:8JESD-30 代码:R-PDSO-G44
长度:28.5 mm内存密度:33554432 bit
内存集成电路类型:MASK ROM内存宽度:16
功能数量:1端子数量:44
字数:2097152 words字数代码:2000000
工作模式:ASYNCHRONOUS最高工作温度:70 °C
最低工作温度:组织:2MX16
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
并行/串行:PARALLEL峰值回流温度(摄氏度):225
认证状态:Not Qualified座面最大高度:3.1 mm
最大供电电压 (Vsup):3.3 V最小供电电压 (Vsup):2.7 V
标称供电电压 (Vsup):3 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:30
宽度:12.6 mmBase Number Matches:1

K3N6U1000C-GC150 数据手册

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K3N6V(U)1000C-GC  
CMOS MASK ROM  
32M-Bit (4Mx8 /2Mx16) CMOS MASK ROM  
FEATURES  
GENERAL DESCRIPTION  
· Switchable organization  
4,194,304x8(byte mode)  
2,097,152x16(word mode)  
· Fast access time  
3.3V Operation : 120ns(Max.)  
3.0V Operation : 150ns(Max.)  
· Supply voltage : single +3.0V/ single +3.3V  
· Current consumption  
The K3N6V(U)1000C-GC is a fully static mask programmable  
ROM fabricated using silicon gate CMOS process technology,  
and is organized either as 4,194,304 x 8 bit(byte mode) or as  
2,097,152 x 16 bit(word mode) depending on BHE voltage  
level.(See mode selection table)  
This device operates with 3.0V or 3.3V power supply, and all  
inputs and outputs are TTL compatible.  
Because of its asynchronous operation, it requires no external  
clock assuring extremely easy operation.  
Operating : 40mA(Max.)  
Standby : 30mA(Max.)  
It is suitable for use in program memory of microprocessor, and  
data memory, character generator.  
· Fully static operation  
· All inputs and outputs TTL compatible  
· Three state outputs  
The K3N6V(U)1000C-GC is packaged in a 44-SOP.  
· Package  
-. K3N6V(U)1000C-GC : 44-SOP-600  
FUNCTIONAL BLOCK DIAGRAM  
PIN CONFIGURATION  
A20  
X
MEMORY CELL  
MATRIX  
(2,097,152x16/  
4,194,304x8)  
BUFFERS  
AND  
DECODER  
A20  
N.C  
A18  
A17  
A7  
1
2
44  
43  
42  
41  
40  
39  
.
.
.
.
.
.
.
.
A19  
A8  
3
4
A9  
A6  
A5  
A10  
A11  
5
6
Y
SENSE AMP.  
BUFFERS  
A4  
7
38 A12  
37 A13  
BUFFERS  
AND  
A3  
8
A14  
36  
A2  
9
DECODER  
A0  
A1  
A15  
35  
10  
11  
12  
13  
14  
15  
16  
17  
18  
A0  
A16  
34  
33  
32  
31  
30  
SOP  
A-1  
BHE  
VSS  
CE  
VSS  
OE  
Q0  
Q8  
Q1  
Q9  
.
.
.
Q15/A-1  
Q7  
CE  
Q0/Q8  
Q7/Q15  
CONTROL  
LOGIC  
29 Q14  
OE  
Q6  
28  
27  
26  
Q13  
Q5  
BHE  
Q2 19  
Q10 20  
25 Q12  
Pin Name  
A0 - A20  
Pin Function  
Address Inputs  
Data Outputs  
Q4  
24  
Q3  
21  
22  
Q11  
VCC  
23  
Q0 - Q14  
Output 15(Word mode)/  
LSB Address(Byte mode)  
K3N6V(U)1000C-GC  
Q15 /A-1  
BHE  
CE  
Word/Byte selection  
Chip Enable  
Output Enable  
Power  
OE  
VCC  
VSS  
N.C  
Ground  
No Connection  

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