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JANTXVF2N7422U

更新时间: 2024-11-05 20:47:07
品牌 Logo 应用领域
英飞凌 - INFINEON /
页数 文件大小 规格书
22页 249K
描述
Transistor

JANTXVF2N7422U 技术参数

是否Rohs认证: 不符合生命周期:Active
包装说明:,Reach Compliance Code:unknown
风险等级:5.64配置:Single
最大漏极电流 (Abs) (ID):22 AFET 技术:METAL-OXIDE SEMICONDUCTOR
JESD-609代码:e0工作模式:ENHANCEMENT MODE
最高工作温度:150 °C极性/信道类型:P-CHANNEL
最大功率耗散 (Abs):4 W子类别:Other Transistors
表面贴装:YES端子面层:Tin/Lead (Sn/Pb)
Base Number Matches:1

JANTXVF2N7422U 数据手册

 浏览型号JANTXVF2N7422U的Datasheet PDF文件第2页浏览型号JANTXVF2N7422U的Datasheet PDF文件第3页浏览型号JANTXVF2N7422U的Datasheet PDF文件第4页浏览型号JANTXVF2N7422U的Datasheet PDF文件第5页浏览型号JANTXVF2N7422U的Datasheet PDF文件第6页浏览型号JANTXVF2N7422U的Datasheet PDF文件第7页 
The documentation and process conversion measures  
necessary to comply with this document shall be  
completed by 10 February 2014.  
INCH-POUND  
MIL-PRF-19500/662F  
10 December 2013  
SUPERSEDING  
MIL-PRF-19500/662E  
11 March 2013  
PERFORMANCE SPECIFICATION SHEET  
SEMICONDUCTOR DEVICE, TRANSISTOR, FIELD EFFECT RADIATION HARDENED  
P-CHANNEL, SILICON, TYPES 2N7422, 2N7422U, 2N7423, AND 2N7423U,  
JANTXVR AND F AND JANSR AND F  
This specification is approved for use by all Departments  
and Agencies of the Department of Defense.  
The requirements for acquiring the product described herein shall consist of  
this specification sheet and MIL-PRF-19500.  
1. SCOPE  
1.1 Scope. This specification covers the performance requirements for a P-channel, enhancement-mode,  
MOSFET, radiation hardened, power transistor. Two levels of product assurance are provided for each device type  
as specified in MIL-PRF-19500, with avalanche energy maximum rating (EAS) and maximum avalanche current (IAS).  
See 6.5 for JANHC and JANKC die versions.  
1.2 Physical dimensions. See figure 1, (TO-254AA), and figure 2, (surface mount, TO-276AB).  
1.3 Maximum ratings. Unless otherwise specified, TA = +25oC.  
Type  
(1)  
PT (2)  
TC =  
PT  
VDS  
VDG  
VGS ID1 (4) (5) ID2 (4) (5)  
IS  
IDM  
(6)  
TJ  
and  
TSTG  
R θ  
(3)  
JC  
TA =  
TC =  
TC =  
+25oC  
+25oC  
+100oC  
+25oC  
A dc  
W
W
V dc  
V dc V dc  
A dc  
-14.0  
-9.0  
A dc A (pk)  
oC  
°C/W  
2N7422  
2N7423  
150  
150  
4.0  
4.0  
0.83 -100  
0.83 -200  
-100  
-200  
-22.0  
-14.0  
-22.0  
-14.0  
-88  
-56  
-55 to  
+150  
±20  
±20  
(1) Unless otherwise noted, electrical characteristics, ratings, and conditions for "U" suffix devices (surface mount)  
are identical to the corresponding non-"U" suffix devices.  
(2) Derate linearly by 1.2 W/°C for TC > +25°C.  
(3) See figure 3, thermal impedance curves.  
(4) The following formula derives the maximum theoretical ID limit. ID is limited by package and internal  
construction.  
-
TJM TC  
( on ) at  
TJM  
=
ID  
(
)
x
(
)
RθJC  
RDS  
(5) See figure 4, maximum drain current graphs.  
(6) IDM = 4 X ID1 as calculated in note (4).  
Comments, suggestions, or questions on this document should be addressed to DLA Land and Maritime,  
ATTN: VAC, P.O. Box 3990, Columbus, OH 43218-3990, or emailed to Semiconductor@dla.mil. Since contact  
information can change, you may want to verify the currency of this address information using the ASSIST  
Online database at https://assist.dla.mil/.  
AMSC N/A  
FSC 5961  
 

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