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JANTXVH2N7481U3

更新时间： 2024-11-06 10:20:43
品牌 Logo 应用领域
英飞凌 - INFINEON /
页数 文件大小 规格书
22页 190K
描述
Power Field-Effect Transistor, N-Channel, Metal-oxide Semiconductor FET

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JANTXVH2N7481U3 数据手册

 浏览型号JANTXVH2N7481U3的Datasheet PDF文件第2页浏览型号JANTXVH2N7481U3的Datasheet PDF文件第3页浏览型号JANTXVH2N7481U3的Datasheet PDF文件第4页浏览型号JANTXVH2N7481U3的Datasheet PDF文件第5页浏览型号JANTXVH2N7481U3的Datasheet PDF文件第6页浏览型号JANTXVH2N7481U3的Datasheet PDF文件第7页 
INCH-POUND  
The documentation and process conversion  
measures necessary to comply with this revision  
shall be completed by 30 November 2010.  
MIL-PRF-19500/703B  
30 August 2010  
SUPERSEDING  
MIL-PRF-19500/703A  
2 July 2004  
PERFORMANCE SPECIFICATION SHEET  
SEMICONDUCTOR DEVICE, FIELD EFFECT RADIATION HARDENED  
(TOTAL DOSE AND SINGLE EVENT EFFECTS)  
TRANSISTOR, N-CHANNEL, SILICON, TYPES 2N7479U3, 2N7480U3, AND 2N7481U3,  
JANTXVR, F, G, AND H AND JANSR, F, G, AND H  
This specification is approved for use by all Departments  
and Agencies of the Department of Defense.  
The requirements for acquiring the product described herein shall consist of  
this specification sheet and MIL-PRF-19500.  
1. SCOPE  
1.1 Scope. This specification covers the performance requirements for a N-Channel, enhancement-mode,  
MOSFET, radiation hardened (total dose and single event effects (SEE)), power transistor. Two levels of product  
assurance are provided for each device type as specified in MIL-PRF-19500, with avalanche energy maximum rating  
(EAS) and maximum avalanche current (IAS).  
1.2 Physical dimensions. See figure 1, surface mount, TO-276AA (SMD-0.5) for U3.  
*
1.3 Maximum ratings. TA = +25°C, unless otherwise specified.  
Type  
PT (1)  
TC =  
+25°C +25°C  
PT  
TA =  
VDS  
VDG  
VGS  
ID1 (3) (4)  
TC  
=+25°C  
ID2 (3) (4)  
TC =  
+100°C  
IS  
IDM (5)  
A (pk)  
TJ  
and  
TSTG  
RθJC  
(2)  
W
W
°C/W  
V dc  
V dc  
V dc  
A dc  
A dc  
A dc  
°C  
2N7479U3  
2N7480U3  
2N7481U3  
75  
75  
75  
1.0  
1.0  
1.0  
1.67  
1.67  
1.67  
30  
60  
30  
60  
22  
22  
22  
22  
21  
16  
22  
22  
22  
88  
88  
88  
±20  
±20  
±20  
-55  
to  
+150  
100  
100  
(1) Derate linearly by 0.6 W/°C for TC > +25°C.  
(2) See figure 2, thermal impedance curves.  
(3) The following formula derives the maximum theoretical ID limit. ID is limited by package and internal construction.  
-
TJM TC  
( on ) at  
TJM  
=
ID  
(
)
x
(
)
RθJC  
RDS  
(4) See figure 3, maximum drain current graph.  
(5) IDM = 4 X ID1 as calculated in note (3).  
* Comments, suggestions, or questions on this document should be addressed to DLA Land and Maritime,  
ATTN: VAC, P.O. Box 3990, Columbus, OH 43218-3990, or emailed to Semiconductor@dscc.dla.mil. Since  
contact information can change, you may want to verify the currency of this address information using the  
ASSIST Online database at https://assist.daps.dla.mil/.  
AMSC N/A  
FSC 5961  
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