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JANSF2N7424U

更新时间: 2024-09-10 21:07:03
品牌 Logo 应用领域
英飞凌 - INFINEON 开关脉冲晶体管
页数 文件大小 规格书
25页 337K
描述
Power Field-Effect Transistor, 48A I(D), 60V, 0.048ohm, 1-Element, P-Channel, Silicon, Metal-oxide Semiconductor FET, HERMETIC SEALED, CERAMIC, SMD2, 3 PIN

JANSF2N7424U 技术参数

是否Rohs认证: 不符合生命周期:Active
包装说明:HERMETIC SEALED, CERAMIC, SMD2, 3 PINReach Compliance Code:compliant
ECCN代码:EAR99风险等级:5.17
Is Samacsys:N其他特性:HIGH RELIABILITY
雪崩能效等级(Eas):500 mJ外壳连接:DRAIN
配置:SINGLE WITH BUILT-IN DIODE最小漏源击穿电压:60 V
最大漏极电流 (ID):48 A最大漏源导通电阻:0.048 Ω
FET 技术:METAL-OXIDE SEMICONDUCTORJESD-30 代码:R-CBCC-N3
JESD-609代码:e0元件数量:1
端子数量:3工作模式:ENHANCEMENT MODE
封装主体材料:CERAMIC, METAL-SEALED COFIRED封装形状:RECTANGULAR
封装形式:CHIP CARRIER峰值回流温度(摄氏度):NOT SPECIFIED
极性/信道类型:P-CHANNEL最大脉冲漏极电流 (IDM):192 A
认证状态:Qualified参考标准:MIL-19500/655
表面贴装:YES端子面层:Tin/Lead (Sn/Pb)
端子形式:NO LEAD端子位置:BOTTOM
处于峰值回流温度下的最长时间:NOT SPECIFIED晶体管应用:SWITCHING
晶体管元件材料:SILICONBase Number Matches:1

JANSF2N7424U 数据手册

 浏览型号JANSF2N7424U的Datasheet PDF文件第2页浏览型号JANSF2N7424U的Datasheet PDF文件第3页浏览型号JANSF2N7424U的Datasheet PDF文件第4页浏览型号JANSF2N7424U的Datasheet PDF文件第5页浏览型号JANSF2N7424U的Datasheet PDF文件第6页浏览型号JANSF2N7424U的Datasheet PDF文件第7页 
INCH-POUND  
The documentation and process conversion  
measures necessary to comply with this revision  
shall be completed by 14 May 2012.  
MIL-PRF-19500/655E  
14 February 2012  
SUPERSEDING  
MIL-PRF-19500/655D  
30 April 2007  
PERFORMANCE SPECIFICATION SHEET  
SEMICONDUCTOR DEVICE, FIELD EFFECT RADIATION HARDENED  
(TOTAL DOSE AND SINGLE EVENT EFFECTS) TRANSISTOR, P-CHANNEL  
SILICON, TYPES 2N7424U, 2N7425U, AND 2N7426U,  
*
JANTXVR AND F AND JANSR AND F  
This specification is approved for use by all Departments  
and Agencies of the Department of Defense.  
The requirements for acquiring the product described herein shall consist of  
this specification sheet and MIL-PRF-19500.  
1. SCOPE  
*
1.1 Scope. This specification covers the performance requirements for a P-Channel, enhancement-mode,  
MOSFET, radiation hardened (total dose and single event effects (SEE)), power transistor. Two levels of product  
assurance are provided for each device type as specified in MIL-PRF-19500, with avalanche energy maximum rating  
(EAS) and maximum avalanche current (IAS). See 6.5 for JANHC and JANKC die versions.  
1.2 Physical dimensions. See figure 1, (surface mount).  
1.3 Maximum ratings. TA = +25°C, unless otherwise specified.  
Type  
PT (1)  
TC =  
+25°C +25°C  
PT  
TA =  
VDS  
VDG  
VGS  
ID1 (3) (4) ID2 (3) (4)  
IS  
IDM (5)  
A (pk)  
TJ  
and  
TSTG  
R θ  
(2)  
JC  
TC =  
+100°C  
TC  
=+25°C  
W
W
V dc  
V dc  
V dc  
A dc  
A dc  
A dc  
°C/W  
°C  
2N7424U  
2N7425U  
2N7426U  
300  
300  
300  
2.5  
2.5  
2.5  
-60  
-60  
-48  
-38  
-29  
-30  
-24  
-18  
-48  
-38  
-29  
-192  
-152  
-108  
0.42  
0.42  
0.42  
±20  
±20  
±20  
-55  
to  
+150  
-100  
-200  
-100  
-200  
(1) Derate linearly by 2.4 W/°C for TC > +25°C.  
(2) See figure 2, thermal impedance curves.  
(3) The following formula derives the maximum theoretical ID limit. ID is limited by package and internal construction.  
(4) See figure 3, maximum drain current graph.  
(5) IDM = 4 X ID1 as calculated in note (3).  
* Comments, suggestions, or questions on this document should be addressed to DLA Land and Maritime,  
ATTN: VAC, P.O. Box 3990, Columbus, OH 43218-3990, or emailed to Semiconductor@dla.mil. Since contact  
information can change, you may want to verify the currency of this address information using the ASSIST  
Online database at https//assist.daps.dla.mil/.  
AMSC N/A  
FSC 5961  
 

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