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IS65WV25616DBLL-45CTLA1 PDF预览

IS65WV25616DBLL-45CTLA1

更新时间: 2024-12-01 12:46:27
品牌 Logo 应用领域
美国芯成 - ISSI 静态存储器
页数 文件大小 规格书
17页 414K
描述
256K x 16 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC SRAM

IS65WV25616DBLL-45CTLA1 数据手册

 浏览型号IS65WV25616DBLL-45CTLA1的Datasheet PDF文件第2页浏览型号IS65WV25616DBLL-45CTLA1的Datasheet PDF文件第3页浏览型号IS65WV25616DBLL-45CTLA1的Datasheet PDF文件第4页浏览型号IS65WV25616DBLL-45CTLA1的Datasheet PDF文件第5页浏览型号IS65WV25616DBLL-45CTLA1的Datasheet PDF文件第6页浏览型号IS65WV25616DBLL-45CTLA1的Datasheet PDF文件第7页 
IS62WV25616DALL/DBLL, IS65WV25616DBLL  
256K x 16 LOW VOLTAGE,  
ULTRA LOW POWER CMOS STATIC SRAM  
JUNE 2013  
FEATURES  
DESCRIPTION  
TheꢀISSIꢀIS62WV25616DALLꢀandꢀIS62/65WV25616DBLLꢀ  
areꢀꢀhigh-speed,ꢀlowꢀpower,ꢀ4MꢀbitꢀSRAMsꢀorganizedꢀasꢀ  
256K words by 16 bits. It is fabricated using ISSI's high-  
performanceCMOStechnology.Thishighlyreliableprocessꢀ  
coupled with innovative circuit design techniques, yields  
high-performance and low power consumption devices.  
•ꢀ High-speed access time: 35, 45, 55 ns  
•ꢀ CMOSꢀlowꢀpowerꢀoperation  
30 mW (typical) operating  
ꢀ 6ꢀµWꢀ(typical)ꢀCMOSꢀstandby  
•ꢀ TTLꢀcompatibleꢀinterfaceꢀlevels  
•ꢀ Singleꢀpowerꢀsupplyꢀꢀ  
When CS1 is HIGH (deselected) or when CS2 is LOW  
(deselcted) or when CS1ꢀisꢀLOW,CS2ꢀisꢀHIGHꢀandꢀbothꢀ  
LB and UB are HIGH, the device assumes a standby mode  
at which the power dissipation can be reduced down with  
CMOSꢀinputꢀlevels.  
1.65V--2.2V Vdd (IS62WV25616DALL)  
2.5V--3.6V Vdd ꢀ(IS62/65WV25616DBLL)  
Easy memory expansion is provided by using Chip Enable  
andOutputEnableinputs.TheactiveLOWWriteEnable(WE)  
controls both writing and reading of the memory.A data byte  
allows Upper Byte (UB)ꢀandꢀLowerꢀByteꢀ(LB) access.  
•ꢀ Fullyꢀstaticꢀoperation:ꢀnoꢀclockꢀorꢀrefresh  
required  
•ꢀ Threeꢀstateꢀoutputs  
•ꢀ Dataꢀcontrolꢀforꢀupperꢀandꢀlowerꢀbytes  
•ꢀ IndustrialꢀandꢀAutomotiveꢀtemperatureꢀsupport  
•ꢀ Lead-freeꢀavailable  
TheꢀIS62WV25616DALLꢀandꢀIS62/65WV25616DBLLꢀareꢀ  
packaged in the JEDEC standard 44-PinꢀTSOPꢀ(TYPEꢀII)  
and 48-pin mini BGA (6mmx8mm).  
•ꢀ 2ꢀCSꢀoptionꢀavailable  
FUNCTIONAL BLOCK DIAGRAM  
256K x 16  
MEMORY ARRAY  
A0-A17  
DECODER  
V
DD  
GND  
I/O0-I/O7  
Lower Byte  
I/O  
DATA  
COLUMN I/O  
CIRCUIT  
I/O8-I/O15  
Upper Byte  
CS2  
CS1  
OE  
CONTROL  
CIRCUIT  
WE  
UB  
LB  
Copyright © 2013 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without  
notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the lat-  
est version of this device specification before relying on any published information and before placing orders for products.  
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be ex-  
pected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon  
Solution, Inc. receives written assurance to its satisfaction, that:  
a.) the risk of injury or damage has been minimized;  
b.) the user assume all such risks; and  
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances  
Integrated Silicon Solution, Inc. — www.issi.com  
1
Rev. D  
06/19/2013  

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