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IS65WV51216EFALL-55BLA3 PDF预览

IS65WV51216EFALL-55BLA3

更新时间: 2024-02-28 14:18:45
品牌 Logo 应用领域
美国芯成 - ISSI 静态存储器内存集成电路
页数 文件大小 规格书
20页 742K
描述
Standard SRAM, 512KX16, 55ns, CMOS, PBGA48, MINIBGA-48

IS65WV51216EFALL-55BLA3 技术参数

生命周期:Active包装说明:VFBGA,
Reach Compliance Code:unknownHTS代码:8542.32.00.41
风险等级:5.73最长访问时间:55 ns
JESD-30 代码:R-PBGA-B48长度:8 mm
内存密度:8388608 bit内存集成电路类型:STANDARD SRAM
内存宽度:16功能数量:1
端子数量:48字数:524288 words
字数代码:512000工作模式:ASYNCHRONOUS
最高工作温度:125 °C最低工作温度:-40 °C
组织:512KX16封装主体材料:PLASTIC/EPOXY
封装代码:VFBGA封装形状:RECTANGULAR
封装形式:GRID ARRAY, VERY THIN PROFILE, FINE PITCH并行/串行:PARALLEL
座面最大高度:1 mm最大供电电压 (Vsup):2.2 V
最小供电电压 (Vsup):1.65 V标称供电电压 (Vsup):1.8 V
表面贴装:YES技术:CMOS
温度等级:AUTOMOTIVE端子形式:BALL
端子节距:0.75 mm端子位置:BOTTOM
宽度:6 mmBase Number Matches:1

IS65WV51216EFALL-55BLA3 数据手册

 浏览型号IS65WV51216EFALL-55BLA3的Datasheet PDF文件第2页浏览型号IS65WV51216EFALL-55BLA3的Datasheet PDF文件第3页浏览型号IS65WV51216EFALL-55BLA3的Datasheet PDF文件第4页浏览型号IS65WV51216EFALL-55BLA3的Datasheet PDF文件第5页浏览型号IS65WV51216EFALL-55BLA3的Datasheet PDF文件第6页浏览型号IS65WV51216EFALL-55BLA3的Datasheet PDF文件第7页 
IS62WV51216EFALL/BLL  
IS65WV51216EFALL/BLL  
JANUARY 2017  
512Kx16 LOW VOLTAGE,  
ULTRA LOW POWER CMOS STATIC RAM with ECC  
KEY FEATURES  
DESCRIPTION  
The ISSI IS62/65WV51216EFALL/BLL are high-speed, low  
power, 8M bit static RAMs organized as 512K words by 16  
bits. It is fabricated using ISSI's high-performance CMOS  
technology and implemented ECC function to improve  
reliability.  
High-speed access time: 45ns, 55ns  
CMOS low power operation  
Operating Current: 36mA (max.)  
CMOS standby Current: 5.8uA (typ.)  
TTL compatible interface levels  
Single power supply  
This highly reliable process coupled with innovative circuit  
design techniques including ECC (SEC-DEC: Single Error  
Correcting-Double Error Detecting),yields high-performance  
and low power consumption devices. When CS1# is HIGH  
(deselected) or when CS2 is LOW (deselected), or when  
CS1# is LOW, CS2 is HIGH and both LB# and UB# are  
HIGH, the device assumes a standby mode at which the  
power dissipation can be reduced down with CMOS input  
levels.  
1.65V-2.2V VDD (IS62/65WV51216EFALL)  
2.2V-3.6V VDD (IS62/65WV51216EFBLL)  
Optional ERR1/ERR2 pin:  
ERR1: indicates 1-bit error detection and  
correction.  
ERR2: indicates 2-bit error detection  
Three state outputs  
Easy memory expansion is provided by using Chip Enable  
and Output Enable inputs. The active LOW Write Enable  
(WE#) controls both writing and reading of the memory. A  
data byte allows Upper Byte (UB#) and Lower Byte (LB#)  
access.  
Commercial, Industrial and Automotive  
temperature support  
Lead-free available  
The IS62/65WV51216EFALL/BLL are packaged in the  
JEDEC standard 48-pin mini BGA (6mm x 8mm), and 44-pin  
TSOP (TYPE II)  
FUNCTIONAL BLOCK DIAGRAM  
Memory  
Memory  
Upper IO  
Array  
Lower IO ECC  
Array  
Array  
512Kx8 512Kx4  
ECC  
Array  
512Kx4  
DECODER  
A0 A18  
512Kx8  
VDD  
VSS  
ERR1  
ERR2  
8
5
8
5
13  
13  
8
8
I/O  
DATA  
CIRCUIT  
I/O0 I/O7  
ECC  
ECC  
Column I/O  
I/O8 I/O15  
CS1#  
CS2  
OE#  
WE#  
UB#  
LB#  
CONTROL  
CIRCUIT  
Copyright © 2016 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time  
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to  
obtain the latest version of this device specification before relying on any published information and before placing orders for products.  
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can  
reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such  
applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that:  
a.) the risk of injury or damage has been minimized;  
b.) the user assume all such risks; and  
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances  
Integrated Silicon Solution, Inc.- www.issi.com  
1
Rev. A  
01/05/2017  

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