IS62WV1288DALL/DBLL
IS65WV1288DALL/DBLLꢀ
READꢀCYCLEꢀSWITCHINGꢀCHARACTERISTICS(1)ꢀ(OverꢀOperatingꢀRange)
ꢀ
ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ
ꢀ
ꢀ 35ꢀns
ꢀ
ꢀ
ꢀ 45ꢀnsꢀꢀ ꢀ
ꢀ 55ꢀnsꢀ ꢀ
ꢀ Symbolꢀ
Parameterꢀ
Min.ꢀ ꢀ Max.ꢀ
35ꢀ ꢀ —ꢀ
—ꢀ ꢀ 35ꢀ
10ꢀ ꢀ —ꢀ
—ꢀ ꢀ 35ꢀ
—ꢀ ꢀ 10ꢀ
—ꢀ ꢀ 10ꢀ
3ꢀ ꢀ —ꢀ
0ꢀ ꢀ 10ꢀꢀ
5ꢀ ꢀ —ꢀ
Min.ꢀ ꢀ Max.ꢀ
Min.ꢀ ꢀ Max.ꢀ ꢀ Unit
ꢀ ꢀ trCꢀ
ReadꢀCycleꢀTimeꢀ
45ꢀ ꢀ —ꢀ
—ꢀ ꢀ 45ꢀ
10ꢀ ꢀ —ꢀ
—ꢀ ꢀ 45ꢀ
—ꢀ ꢀ 20ꢀ
—ꢀ ꢀ 15ꢀ
55ꢀ ꢀ —ꢀ
—ꢀ ꢀ 55ꢀ
10ꢀ ꢀ —ꢀ
—ꢀ ꢀ 55ꢀ
—ꢀ ꢀ 25ꢀ
—ꢀ ꢀ 20ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ns
ns
ns
ns
ns
ns
ns
ns
ns
ꢀ ꢀ tAAꢀ
AddressꢀAccessꢀTimeꢀ
OutputꢀHoldꢀTimeꢀ
ꢀ ꢀ tOhAꢀ
ꢀ ꢀ tACs1/tACs2ꢀ
ꢀ ꢀ tdOeꢀ
CS1/CS2ꢀAccessꢀTimeꢀ
OEꢀAccessꢀTimeꢀ
(2)
ꢀ ꢀ thzOe ꢀ
OEꢀtoꢀHigh-ZꢀOutputꢀ
OEꢀtoꢀLow-ZꢀOutputꢀ
(2)
ꢀ ꢀ tLzOe ꢀ
5ꢀ
ꢀ
—ꢀ
5ꢀ
0ꢀ
ꢀ
ꢀ
—ꢀ
20ꢀ
(2)
ꢀ ꢀ thzCs1/thzCs2 ꢀ CS1/CS2ꢀtoꢀHigh-ZꢀOutputꢀ
0ꢀ ꢀ 15ꢀ
10ꢀ ꢀ —ꢀ
(2)
ꢀ ꢀ tLzCs1/tLzCs2 ꢀ CS1/CS2ꢀtoꢀLow-ZꢀOutputꢀ
10ꢀ ꢀ —ꢀ
Notes:ꢀ
1.ꢀ Testꢀconditionsꢀassumeꢀsignalꢀtransitionꢀtimesꢀofꢀ5ꢀnsꢀorꢀless,ꢀtimingꢀreferenceꢀlevelsꢀofꢀ0.9V/1.5V,ꢀinputꢀpulseꢀlevelsꢀofꢀ0.4ꢀtoꢀ
Vdd-0.2V/Vdd-0.3VꢀandꢀoutputꢀloadingꢀspecifiedꢀinꢀFigureꢀ1.
2.ꢀ TestedꢀwithꢀtheꢀloadꢀinꢀFigureꢀ2.ꢀTransitionꢀisꢀmeasuredꢀ 500ꢀmVꢀfromꢀsteady-stateꢀvoltage.ꢀNotꢀ100%ꢀtested.
Integrated Silicon Solution, Inc. — www.issi.comꢀ
7
Rev.ꢀ B
12/01/2010