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IS61WV51216EDBLL PDF预览

IS61WV51216EDBLL

更新时间: 2024-11-13 01:23:43
品牌 Logo 应用领域
美国芯成 - ISSI /
页数 文件大小 规格书
19页 921K
描述
TTL compatible inputs and outputs

IS61WV51216EDBLL 数据手册

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IS61WV51216EDALL  
IS61/64WV51216EDBLL  
512K x 16 HIGH-SPEED ASYNCHRONOUS  
CMOS STATIC RAM WITH ECC  
FEBRUARY 2013  
FEATURES  
DESCRIPTION  
•ꢀ High-speedꢀaccessꢀtimes:ꢀ8,ꢀ10,ꢀ20ꢀns  
•ꢀ High-performance,ꢀlow-powerꢀCMOSꢀprocess  
•ꢀ Multipleꢀcenterꢀpowerꢀandꢀgroundꢀpinsꢀforꢀgreaterꢀ  
noise immunity  
•ꢀ Easy memory expansion with CE and OE options  
•ꢀ CE power-down  
TheꢀISSIꢀꢀIS61WV51216EDALLꢀandꢀ  
IS61/64WV51216EDBLLꢀareꢀhigh-speed,ꢀ8M-bitꢀstaticꢀ  
RAMsꢀorganizedꢀasꢀ512Kꢀwordsꢀbyꢀ16ꢀbits.ꢀItꢀisꢀfabri-  
cated using ISSI'sꢀhigh-performanceꢀCMOSꢀtechnology.ꢀ  
Thisꢀhighlyꢀreliableꢀprocessꢀcoupledꢀwithꢀinnovativeꢀ  
circuit design techniques, yields high-performance and  
low power consumption devices.  
•ꢀ Fullyꢀstaticꢀoperation:ꢀnoꢀclockꢀorꢀrefreshꢀ  
When CEꢀisꢀHIGHꢀ(deselected),ꢀtheꢀdeviceꢀassumesꢀ  
a standby mode at which the power dissipation can be  
reducedꢀdownꢀwithꢀCMOSꢀinputꢀlevels.  
required  
•ꢀ TTLꢀcompatibleꢀinputsꢀandꢀoutputs  
•ꢀ SingleꢀPowerꢀSupply  
– Vddꢀ=ꢀ1.65Vꢀtoꢀ2.2Vꢀ(IS61WV51216EDALL)  
– Vddꢀ=ꢀ2.4Vꢀtoꢀ3.6Vꢀ(IS61/64WV51216EDBLL)  
•ꢀ Packagesꢀavailable:  
Easy memory expansion is provided by using Chip En-  
ableꢀandꢀOutputꢀEnableꢀinputs,ꢀCE and OE.ꢀTheꢀactiveꢀ  
LOWꢀWriteꢀEnableꢀ(WE) controls both writing and read-  
ing of the memory. A data byte allows Upper Byte (UB)  
andꢀLowerꢀByteꢀ(LB) access.  
ꢀ48-ballꢀminiBGAꢀꢀ(6mmꢀxꢀ8mm)  
ꢀ –ꢀꢀ44-pinꢀTSOPꢀ(TypeꢀII)ꢀ  
•ꢀ IndustrialꢀandꢀAutomotiveꢀTemperatureꢀSupport  
•ꢀ Lead-freeꢀavailable  
•ꢀ Dataꢀcontrolꢀforꢀupperꢀandꢀlowerꢀbytes  
TheꢀdeviceꢀisꢀpackagedꢀinꢀtheꢀJEDECꢀstandardꢀ44-pinꢀ  
TSOPꢀTypeꢀIIꢀandꢀ48-pinꢀMiniꢀBGAꢀ(6mmꢀxꢀ8mm).  
FUNCTIONAL BLOCK DIAGRAM  
Memory  
Lower IO  
Array-  
Memory  
Upper IO  
Array-  
A0-A18  
ECC  
Array-  
512K  
x4  
ECC  
Array-  
512K  
x4  
Decoder  
512Kx8  
512Kx8  
8
4
8
4
8
8
8
8
12  
12  
IO0-7  
ECC  
ECC  
I/O Data  
Circuit  
Column I/O  
IO8-15  
/CE  
/OE  
/WE  
/UB  
/LB  
Control  
Circuit  
Copyright © 2013 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without  
notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the lat-  
est version of this device specification before relying on any published information and before placing orders for products.  
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reason-  
ably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications  
unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that:  
a.) the risk of injury or damage has been minimized;  
b.) the user assume all such risks; and  
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances  
Integrated Silicon Solution, Inc. — www.issi.com  
1
Rev. A  
02/20/2013  

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