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IS61WV51216EDBLL-8TLI

更新时间： 2024-11-12 19:46:43
品牌 Logo 应用领域
美国芯成 - ISSI 静态存储器光电二极管内存集成电路
页数 文件大小 规格书
19页 711K
描述
Standard SRAM, 512KX16, 8ns, CMOS, PDSO44, 0.400 INCH, LEAD FREE, TSOP2-44

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IS61WV51216EDBLL-8TLI 技术参数

是否Rohs认证： 符合生命周期：Active
包装说明：TSOP2, TSOP44,.46,32Reach Compliance Code：compliant
Factory Lead Time：8 weeks风险等级：2.22
最长访问时间：8 nsI/O 类型：COMMON
JESD-30 代码：R-PDSO-G44长度：18.41 mm
内存密度：8388608 bit内存集成电路类型：STANDARD SRAM
内存宽度：16功能数量：1
端子数量：44字数：524288 words
字数代码：512000工作模式：ASYNCHRONOUS
最高工作温度：85 °C最低工作温度：-40 °C
组织：512KX16输出特性：3-STATE
封装主体材料：PLASTIC/EPOXY封装代码：TSOP2
封装等效代码：TSOP44,.46,32封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, THIN PROFILE并行/串行：PARALLEL
电源：2.5/3.3 V认证状态：Not Qualified
座面最大高度：1.2 mm最大待机电流：0.015 A
最小待机电流：2 V子类别：SRAMs
最大压摆率：0.055 mA最大供电电压 (Vsup)：3.6 V
最小供电电压 (Vsup)：2.4 V标称供电电压 (Vsup)：3 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子形式：GULL WING
端子节距：0.8 mm端子位置：DUAL
宽度：10.16 mmBase Number Matches：1

IS61WV51216EDBLL-8TLI 数据手册

 浏览型号IS61WV51216EDBLL-8TLI的Datasheet PDF文件第2页浏览型号IS61WV51216EDBLL-8TLI的Datasheet PDF文件第3页浏览型号IS61WV51216EDBLL-8TLI的Datasheet PDF文件第4页浏览型号IS61WV51216EDBLL-8TLI的Datasheet PDF文件第5页浏览型号IS61WV51216EDBLL-8TLI的Datasheet PDF文件第6页浏览型号IS61WV51216EDBLL-8TLI的Datasheet PDF文件第7页 
IS61WV51216EDALL  
IS61/64WV51216EDBLL  
512K x 16 HIGH-SPEED ASYNCHRONOUS  
CMOS STATIC RAM WITH ECC  
FEBRUARY 2013  
FEATURES  
DESCRIPTION  
•ꢀ High-speedꢀaccessꢀtimes:ꢀ8,ꢀ10,ꢀ20ꢀns  
•ꢀ High-performance,ꢀlow-powerꢀCMOSꢀprocess  
•ꢀ Multipleꢀcenterꢀpowerꢀandꢀgroundꢀpinsꢀforꢀgreaterꢀ  
noise immunity  
•ꢀ Easy memory expansion with CE and OE options  
•ꢀ CE power-down  
TheꢀISSIꢀꢀIS61WV51216EDALLꢀandꢀ  
IS61/64WV51216EDBLLꢀareꢀhigh-speed,ꢀ8M-bitꢀstaticꢀ  
RAMsꢀorganizedꢀasꢀ512Kꢀwordsꢀbyꢀ16ꢀbits.ꢀItꢀisꢀfabri-  
cated using ISSI'sꢀhigh-performanceꢀCMOSꢀtechnology.ꢀ  
Thisꢀhighlyꢀreliableꢀprocessꢀcoupledꢀwithꢀinnovativeꢀ  
circuit design techniques, yields high-performance and  
low power consumption devices.  
•ꢀ Fullyꢀstaticꢀoperation:ꢀnoꢀclockꢀorꢀrefreshꢀ  
When CEꢀisꢀHIGHꢀ(deselected),ꢀtheꢀdeviceꢀassumesꢀ  
a standby mode at which the power dissipation can be  
reducedꢀdownꢀwithꢀCMOSꢀinputꢀlevels.  
required  
•ꢀ TTLꢀcompatibleꢀinputsꢀandꢀoutputs  
•ꢀ SingleꢀPowerꢀSupply  
– Vddꢀ=ꢀ1.65Vꢀtoꢀ2.2Vꢀ(IS61WV51216EDALL)  
– Vddꢀ=ꢀ2.4Vꢀtoꢀ3.6Vꢀ(IS61/64WV51216EDBLL)  
•ꢀ Packagesꢀavailable:  
Easy memory expansion is provided by using Chip En-  
ableꢀandꢀOutputꢀEnableꢀinputs,ꢀCE and OE.ꢀTheꢀactiveꢀ  
LOWꢀWriteꢀEnableꢀ(WE) controls both writing and read-  
ing of the memory. A data byte allows Upper Byte (UB)  
andꢀLowerꢀByteꢀ(LB) access.  
–
ꢀ48-ballꢀminiBGAꢀꢀ(6mmꢀxꢀ8mm)  
ꢀ –ꢀꢀ44-pinꢀTSOPꢀ(TypeꢀII)ꢀ  
•ꢀ IndustrialꢀandꢀAutomotiveꢀTemperatureꢀSupport  
•ꢀ Lead-freeꢀavailable  
•ꢀ Dataꢀcontrolꢀforꢀupperꢀandꢀlowerꢀbytes  
TheꢀdeviceꢀisꢀpackagedꢀinꢀtheꢀJEDECꢀstandardꢀ44-pinꢀ  
TSOPꢀTypeꢀIIꢀandꢀ48-pinꢀMiniꢀBGAꢀ(6mmꢀxꢀ8mm).  
FUNCTIONAL BLOCK DIAGRAM  
Memory  
Lower IO  
Array-  
Memory  
Upper IO  
Array-  
A0-A18  
ECC  
Array-  
512K  
x4  
ECC  
Array-  
512K  
x4  
Decoder  
512Kx8  
512Kx8  
8
4
8
4
8
8
8
8
12  
12  
IO0-7  
ECC  
ECC  
I/O Data  
Circuit  
Column I/O  
IO8-15  
/CE  
/OE  
/WE  
/UB  
/LB  
Control  
Circuit  
Copyright © 2013 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without  
notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the lat-  
est version of this device specification before relying on any published information and before placing orders for products.  
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reason-  
ably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications  
unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that:  
a.) the risk of injury or damage has been minimized;  
b.) the user assume all such risks; and  
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances  
Integrated Silicon Solution, Inc. — www.issi.com  
1
Rev. A  
02/20/2013  
1234567...19

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