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IS46R83200B PDF预览

IS46R83200B

更新时间: 2024-11-23 12:31:15
品牌 Logo 应用领域
美国芯成 - ISSI 动态存储器双倍数据速率
页数 文件大小 规格书
41页 932K
描述
32Mx8, 16Mx16 256Mb DDR Synchronous DRAM

IS46R83200B 数据手册

 浏览型号IS46R83200B的Datasheet PDF文件第2页浏览型号IS46R83200B的Datasheet PDF文件第3页浏览型号IS46R83200B的Datasheet PDF文件第4页浏览型号IS46R83200B的Datasheet PDF文件第5页浏览型号IS46R83200B的Datasheet PDF文件第6页浏览型号IS46R83200B的Datasheet PDF文件第7页 
IS43R83200B, IS46R83200B  
IS43R16160B, IS46R16160B  
32Mx8, 16Mx16  
256Mb DDR Synchronous DRAM  
AUGUST 2010  
FEATURES:  
•ꢀ Vd d =Vd d q = 2.5V+0.2V (-5, -6, -75)  
•ꢀ Double data rate architecture; two data transfers  
per clock cycle.  
•ꢀ Bidirectional , data strobe (DQS) is transmitted/  
received with data  
•ꢀ Differential clock input (CLK and /CLK)  
DESCRIPTION:  
IS43/46R83200B is a 4-bank x 8,388,608-word x8bit,  
IS43/46R16160B is a 4-bank x 4,194,304-word x 16bit  
double data rate synchronous DRAM , with SSTL_2  
interface. All control and address signals are referenced  
to the rising edge of CLK. Input data is registered on  
both edges of data strobe, and output data and data  
strobe are referenced on both edges of CLK. The device  
achieves very high speed clock rate up to 200 MHz.  
•ꢀ DLL aligns DQ and DQS transitions with CLK  
transitions edges of DQS  
•ꢀ Commands entered on each positive CLK edge;  
•ꢀ Data and data mask referenced to both edges of  
KEY TIMING PARAMETERS  
Parameter  
-5  
-6  
-75 Unit  
DQS  
Clk Cycle Time  
•ꢀ 4 bank operation controlled by BA0 , BA1  
CAS Latency = 3  
CAS Latency = 2.5  
CAS Latency = 2  
5
5
7.5  
6
6
7.5  
7.5  
7.5  
7.5  
ns  
ns  
ns  
(Bank Address)  
•ꢀ /CAS latency -2.0 / 2.5 / 3.0 (programmable) ;  
Burst length -2 / 4 / 8 (programmable)  
Burst type -Sequential / Interleave (program-  
mable)  
Clk Frequency  
CAS Latency = 3  
CAS Latency = 2.5  
CAS Latency = 2  
200  
200  
133  
167  
167  
133  
133 MHz  
133 MHz  
133 MHz  
•ꢀ Auto precharge/ All bank precharge controlled  
by A10  
Access Time from Clock  
CAS Latency = 3  
•ꢀ 8192 refresh cycles / 64ms (4 banks concurrent  
+0.70 +0.70 +0.75 ns  
refresh)  
CAS Latency = 2.5 +0.70 +0.70 +0.75 ns  
CAS Latency = 2  
•ꢀ Auto refresh and Self refresh  
+0.75 +0.75 +0.75 ns  
•ꢀ Row address A0-12 / Column address A0-9(x8)/  
A0-8(x16)  
•ꢀ SSTL_2 Interface  
•ꢀ Package:  
ADDRESS TABLE  
Parameter  
32M x 8  
16M x 16  
66-pin TSOP II (x8 and x16)  
60-ball TF-BGA (x16 only)  
Configuration  
8M x 8 x 4  
banks  
4M x 16 x 4  
banks  
Bank Address Pins  
BA0, BA1  
BA0, BA1  
•ꢀ Temperature Range:  
Commercial (0oC to +70oC)  
Industrial (-40oC to +85oC)  
Automotive (-40oC to +85oC)  
Autoprecharge Pins  
Row Addresses  
Column Addresses  
Refresh Count  
A10/AP  
A0 – A12  
A0 – A9  
A10/AP  
A0 – A12  
A0 – A8  
8192 / 64ms 8192 / 64ms  
Copyright © 2010 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without  
notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the  
latest version of this device specification before relying on any published information and before placing orders for products.  
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reason-  
ably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications  
unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that:  
a.) the risk of injury or damage has been minimized;  
b.) the user assume all such risks; and  
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances  
Integrated Silicon Solution, Inc.  
1
Rev. E  
08/13/2010  

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