Datasheet > IS46R86400D-6TLA1-TR

IS46R86400D-6TLA1-TR

更新时间： 2024-11-19 19:18:35

品牌	Logo	应用领域
美国芯成 - ISSI		时钟动态存储器光电二极管内存集成电路
页数	文件大小	规格书
33页	978K
描述
Cache DRAM Module, 64MX8, 0.7ns, CMOS, PDSO66, 0.400 INCH, LEAD FREE, TSOP2-66

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IS46R86400D-6TLA1-TR 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Not Recommended	包装说明：	0.400 INCH, LEAD FREE, TSOP2-66
Reach Compliance Code：	compliant	Factory Lead Time：	10 weeks
风险等级：	5.48	访问模式：	FOUR BANK PAGE BURST
最长访问时间：	0.7 ns	其他特性：	AUTO/SELF REFRESH
最大时钟频率 (fCLK)：	166 MHz	I/O 类型：	COMMON
交错的突发长度：	2,4,8	JESD-30 代码：	R-PDSO-G66
JESD-609代码：	e3	长度：	22.22 mm
内存密度：	536870912 bit	内存集成电路类型：	CACHE DRAM MODULE
内存宽度：	8	湿度敏感等级：	1
功能数量：	1	端口数量：	1
端子数量：	66	字数：	67108864 words
字数代码：	64000000	工作模式：	SYNCHRONOUS
最高工作温度：	85 °C	最低工作温度：	-40 °C
组织：	64MX8	输出特性：	3-STATE
封装主体材料：	PLASTIC/EPOXY	封装代码：	TSOP2
封装等效代码：	TSSOP66,.46	封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE, THIN PROFILE	峰值回流温度（摄氏度）：	225
电源：	2.5 V	认证状态：	Not Qualified
刷新周期：	8192	筛选级别：	AEC-Q100
座面最大高度：	1.2 mm	自我刷新：	YES
连续突发长度：	2,4,8	最大待机电流：	0.025 A
子类别：	DRAMs	最大压摆率：	0.37 mA
最大供电电压 (Vsup)：	2.7 V	最小供电电压 (Vsup)：	2.3 V
标称供电电压 (Vsup)：	2.5 V	表面贴装：	YES
技术：	CMOS	温度等级：	INDUSTRIAL
端子面层：	Matte Tin (Sn)	端子形式：	GULL WING
端子节距：	0.65 mm	端子位置：	DUAL
处于峰值回流温度下的最长时间：	NOT SPECIFIED	宽度：	10.16 mm
Base Number Matches：	1

IS46R86400D-6TLA1-TR 数据手册

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IS43/46R86400D

IS43/46R16320D, IS43/46R32160D

16Mx32, 32Mx16, 64Mx8

512Mb DDR SDRAM

MAY 2015

FEATURES

DEVICE OVERVIEW

•ꢀ VDDꢀandꢀVDDQ:ꢀ2.5Vꢀ±ꢀ0.2Vꢀ(-6)

•ꢀ VDDꢀandꢀVDDQ:ꢀ2.6Vꢀ±ꢀ0.1Vꢀ(-5)

•ꢀ SSTL_2ꢀcompatibleꢀI/O

ISSI’sꢀ512-MbitꢀDDRꢀSDRAMꢀachievesꢀhighꢀspeedꢀdataꢀ

transfer using pipeline architecture and two data word

accessesꢀperꢀclockꢀcycle.ꢀTheꢀ536,870,912-bitꢀmemoryꢀ

arrayꢀisꢀinternallyꢀorganizedꢀasꢀfourꢀbanksꢀofꢀ128Mbꢀtoꢀ

allowꢀconcurrentꢀoperations.ꢀTheꢀpipelineꢀallowsꢀReadꢀ

and Write burst accesses to be virtually continuous, with

theꢀoptionꢀtoꢀconcatenateꢀorꢀtruncateꢀtheꢀbursts.ꢀTheꢀ

programmable features of burst length, burst sequence

andꢀCASꢀlatencyꢀenableꢀfurtherꢀadvantages.ꢀTheꢀdeviceꢀ

isꢀavailableꢀinꢀ8-bit,ꢀ16-bitꢀandꢀ32-bitꢀdataꢀwordꢀsizeꢀ

InputꢀdataꢀisꢀregisteredꢀonꢀtheꢀI/Oꢀpinsꢀonꢀbothꢀedgesꢀ

ofꢀDataꢀStrobeꢀsignal(s),ꢀwhileꢀoutputꢀdataꢀisꢀreferencedꢀ

toꢀbothꢀedgesꢀofꢀDataꢀStrobeꢀandꢀbothꢀedgesꢀofꢀCLK.ꢀ

CommandsꢀareꢀregisteredꢀonꢀtheꢀpositiveꢀedgesꢀofꢀCLK.ꢀ

•ꢀ Double-dataꢀrateꢀarchitecture;ꢀtwoꢀdataꢀtransfersꢀ

per clock cycle

•ꢀ Bidirectional,ꢀdataꢀstrobeꢀ(DQS)ꢀisꢀtransmitted/

received with data, to be used in capturing data

at the receiver

•ꢀ DQSꢀisꢀedge-alignedꢀwithꢀdataꢀforꢀREADsꢀandꢀ

centre-alignedꢀwithꢀdataꢀforꢀWRITEs

•ꢀ Differentialꢀclockꢀinputsꢀ(CKꢀandꢀCK)

•ꢀ DLLꢀalignsꢀDQꢀandꢀDQSꢀtransitionsꢀwithꢀCKꢀ

transitions

•ꢀ CommandsꢀenteredꢀonꢀeachꢀpositiveꢀCKꢀedge;ꢀ

data and data mask referenced to both edges of

DQS

AnꢀAutoꢀRefreshꢀmodeꢀisꢀprovided,ꢀalongꢀwithꢀaꢀSelfꢀ

Refreshꢀmode.ꢀAllꢀI/OsꢀareꢀSSTL_2ꢀcompatible.

ADDRESS TABLE

•ꢀ Fourꢀinternalꢀbanksꢀforꢀconcurrentꢀoperation

Parameter

16M x 32

32M x 16

64M x 8

•ꢀ DataꢀMaskꢀforꢀwriteꢀdata.ꢀDMꢀmasksꢀwriteꢀdataꢀ

at both rising and falling edges of data strobe

Conﬁguration 4Mꢀxꢀ32ꢀxꢀ4ꢀ

8Mꢀxꢀ16ꢀxꢀ4ꢀ

16Mꢀxꢀ8ꢀxꢀ4ꢀ

banks

•ꢀ BurstꢀLength:ꢀ2,ꢀ4ꢀandꢀ8

BankꢀAddressꢀ BA0,ꢀBA1

Pins

BA0,ꢀBA1

•ꢀ BurstꢀType:ꢀSequentialꢀandꢀInterleaveꢀmode

•ꢀ ProgrammableꢀCASꢀlatency:ꢀ2,ꢀ2.5ꢀandꢀ3ꢀ

•ꢀ AutoꢀRefreshꢀandꢀSelfꢀRefreshꢀModes

•ꢀ AutoꢀPrecharge

Autoprecharge A8/AP

Pins

A10/AP

RowꢀAddress 8K(A0ꢀ–ꢀA12) 8K(A0ꢀ–ꢀA12) 8K(A0ꢀ–ꢀA12)

•ꢀ T_RASꢀLockoutꢀSupportedꢀ(t_RAP= t_RCD

)

Column

Address

512(A0ꢀ–ꢀA7,ꢀ 1K(A0ꢀ–ꢀA9)

A9)

2K(A0ꢀ–ꢀA9,ꢀ

A11)

OPTIONS

RefreshꢀCount

Com./Ind./A1 8Kꢀ/ꢀ64ms

A2 8Kꢀ/ꢀ16ms

•ꢀ Conﬁguration(s):ꢀ16Mx32,ꢀ32Mx16,ꢀandꢀ64Mx8

8Kꢀ/ꢀ64ms

8Kꢀ/ꢀ16ms

8Kꢀ/ꢀ64ms

8Kꢀ/ꢀ16ms

•ꢀ Package(s):ꢀ144ꢀBallꢀBGAꢀ(x32),ꢀ66-pinꢀTSOP-IIꢀ

(x8,ꢀx16),ꢀandꢀ60ꢀBallꢀBGAꢀ(x8,ꢀx16)

•ꢀ Lead-freeꢀpackage

•ꢀꢀ TemperatureꢀRange:ꢀ

ꢀ Commercialꢀ(0°Cꢀtoꢀ+70°C)

ꢀ Industrialꢀ(-40°Cꢀtoꢀ+85°C)

Automotive,ꢀA1ꢀ(-40°Cꢀtoꢀ+85°C)

Automotive,ꢀA2ꢀ(-40°Cꢀtoꢀ+105°C)

KEY TIMING PARAMETERS

Speed Grade

-5

200ꢀ 167ꢀ

ckꢀMaxꢀCLꢀ=ꢀ2.5ꢀ 167ꢀ 167ꢀ

ckꢀMaxꢀCLꢀ=ꢀ2ꢀ 133ꢀ 133ꢀ

-6

Units

ckꢀMaxꢀCLꢀ=ꢀ3ꢀ

ꢀ

MHz

notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the lat-

est version of this device speciﬁcation before relying on any published information and before placing orders for products.

Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reason-

ably be expected to cause failure of the life support system or to signiﬁcantly affect its safety or effectiveness. Products are not authorized for use in such applications

unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that:

a.) the risk of injury or damage has been minimized;

b.) the user assume all such risks; and

c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances

Integrated Silicon Solution, Inc.

Rev. D

05/18/2015

12 3 4 5 6 7...33

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与IS46R86400D-6TLA1-TR相关器件

型号	品牌	获取价格	描述	数据表
IS46TR16128A-125KBLA1	ISSI	获取价格	256Mx8, 128Mx16 2Gb DDR3 SDRAM
IS46TR16128A-125KBLA2	ISSI	获取价格	256Mx8, 128Mx16 2Gb DDR3 SDRAM
IS46TR16128A-15HBLA1	ISSI	获取价格	256Mx8, 128Mx16 2Gb DDR3 SDRAM
IS46TR16128A-15HBLA2	ISSI	获取价格	256Mx8, 128Mx16 2Gb DDR3 SDRAM
IS46TR16128A-187FBLA1	ISSI	获取价格	256Mx8, 128Mx16 2Gb DDR3 SDRAM
IS46TR16128A-187FBLA2	ISSI	获取价格	256Mx8, 128Mx16 2Gb DDR3 SDRAM
IS46TR16128AL-125KBLA1	ISSI	获取价格	256Mx8, 128Mx16 2Gb DDR3 SDRAM
IS46TR16128AL-125KBLA2	ISSI	获取价格	256Mx8, 128Mx16 2Gb DDR3 SDRAM
IS46TR16128AL-15HBLA1	ISSI	获取价格	256Mx8, 128Mx16 2Gb DDR3 SDRAM
IS46TR16128AL-15HBLA2	ISSI	获取价格	256Mx8, 128Mx16 2Gb DDR3 SDRAM

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