Datasheet > IS43R32800B-5BLI

IS43R32800B-5BLI

更新时间： 2024-10-28 00:52:19

品牌	Logo	应用领域
美国芯成 - ISSI		/
页数	文件大小	规格书
39页	556K
描述
Differential clock input

阅读下载

中文翻译

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

IS43R32800B-5BLI 数据手册

IS43R32800B

8Mx32

PRELIMINARY INFORMATION

MAY 2008

256Mb DDR Synchronous DRAM

FEATURES

DESCRIPTION:

IS43R32800B is a 4-bank x 2,097,152-word x32bit

Double Data Rate Synchronous DRAM, with SSTL_2

interface. All control and address signals are referenced

to the rising edge of CLK. Input data is registered on

both edges of data strobe, and output data and data

strobe are referenced on both edges of CLK. The

IS43R32800B achieves very high speed clock rate up to

200 MHz. It is packaged in 144-ball FBGA.

•ꢀ Vd d /Vd d q =2.5V+0.2V (-5, -6, -75)

•ꢀ Double data rate architecture; two data transfers

per clock cycle

•ꢀ Bidirectional, data strobe (DQS) is transmitted/

received with data

•ꢀ Differential clock input (CLK and /CLK)

•ꢀ DLL aligns DQ and DQS transitions with CLK

transitions edges of DQS

•ꢀ Commands entered on each positive CLK edge;

•ꢀ Data and data mask referenced to both edges of

KEY TIMING PARAMETERS

DQS

Parameter

-5

-6

-75 Unit

•ꢀ 4 bank operation controlled by BA0, BA1 (Bank

Clk Cycle Time

Address)

CAS Latency = 3

CAS Latency = 2.5

CAS Latency = 2

7.5

•ꢀ /CAS latency –2.0/2.5/3.0 (programmable)

•ꢀ Burst length - 2/4/8 (programmable)

•ꢀ Burst type - Sequential/ Interleave (program-

Clk Frequency

mable)

CAS Latency = 3

CAS Latency = 2.5

CAS Latency = 2

200

143

167

143

143 MHz

•ꢀ Auto precharge / All bank precharge controlled

by A8

Access Time from Clock

CAS Latency = 3

•ꢀ 4096 refresh cycles/ 64ms (4 banks concurrent

+0.70 +0.70 +0.70 ns

refresh)

CAS Latency = 2.5 +0.70 +0.70 +0.70 ns

CAS Latency = 2 +0.75 +0.75 +0.70 ns

•ꢀ Auto refresh and Self refresh

•ꢀ Row address A0-11/ Column address A0-7, A9-

SSTL_2 Interface

•ꢀ Package 144-ball FBGA

•ꢀ Available in Industrial Temperature

•ꢀ Temperature Range:

Commercial (0^oC to +70^oC)

Industrial (-40^oC to +85^oC)

ADDRESS TABLE

Parameter

8M x 32

Conﬁguration

2M x 32 x 4 banks

BA0, BA1

Bank Address Pins

Autoprecharge Pins

Row Addresses

Column Addresses

Refresh Count

A8/AP

A0 – A11

A0 – A7, A9

4096 / 64ms

notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the lat-

est version of this device speciﬁcation before relying on any published information and before placing orders for products.

Integrated Silicon Solution, Inc. — www.issi.com

Rev. 00D

03/19/08

12 3 4 5 6 7...39

中文翻译

下载PDF

与IS43R32800B-5BLI相关器件

型号	品牌	获取价格	描述	数据表
IS43R32800B-6B	ISSI	获取价格	Differential clock input
IS43R32800B-6BI	ISSI	获取价格	Differential clock input
IS43R32800B-6BL	ISSI	获取价格	DDR DRAM, 8MX32, 0.7ns, CMOS, PBGA144, 12 X 12 MM, 0.80 MM PITCH, LEAD FREE, MINI, FBGA-14
IS43R32800B-6BLI	ISSI	获取价格	DDR DRAM, 8MX32, 0.7ns, CMOS, PBGA144, 12 X 12 MM, 0.80 MM PITCH, LEAD FREE, MINI, FBGA-14
IS43R32800B-75B	ISSI	获取价格	Differential clock input
IS43R32800B-75BI	ISSI	获取价格	Differential clock input
IS43R32800B-75BL	ISSI	获取价格	Differential clock input
IS43R32800B-75BLI	ISSI	获取价格	Differential clock input
IS43R32800D-5B	ISSI	获取价格	IC DRAM 256M PARALLEL 144LFBGA
IS43R32800D-5BI	ISSI	获取价格	8Mx32, 16Mx16, 32Mx8 256Mb DDR SDRAM

与IS43R32800B-5BLI相关文章

三星深化印度制造布局，供应链本地化进程加速
2024-10-29

11
芯擎科技“星辰一号”自动驾驶芯片点亮成功，2025年量产在即
2024-10-29

10
纳微科技震撼发布GaNSlim革新氮化镓功率芯片
2024-10-18

37
意法半导体发布第四代SiC技术，助力电动汽车电驱
2024-10-15

45

产品中心

服务支持

精选活动

关于我们

帮助中心

IS43R32800B-5BLI

IS43R32800B-5BLI 数据手册

与IS43R32800B-5BLI相关器件

与IS43R32800B-5BLI相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

IS43R32800B-5BLI

IS43R32800B-5BLI 数据手册

与IS43R32800B-5BLI相关器件

与IS43R32800B-5BLI相关文章

您还可以找

您在本页遇到什么问题？