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IS41C85120-60K-TR PDF预览

IS41C85120-60K-TR

更新时间: 2024-09-19 03:27:15
品牌 Logo 应用领域
美国芯成 - ISSI 动态存储器
页数 文件大小 规格书
19页 144K
描述
DRAM

IS41C85120-60K-TR 技术参数

生命周期:Active包装说明:,
Reach Compliance Code:compliant风险等级:5.84

IS41C85120-60K-TR 数据手册

 浏览型号IS41C85120-60K-TR的Datasheet PDF文件第2页浏览型号IS41C85120-60K-TR的Datasheet PDF文件第3页浏览型号IS41C85120-60K-TR的Datasheet PDF文件第4页浏览型号IS41C85120-60K-TR的Datasheet PDF文件第5页浏览型号IS41C85120-60K-TR的Datasheet PDF文件第6页浏览型号IS41C85120-60K-TR的Datasheet PDF文件第7页 
®
IS41C85120  
IS41LV85120  
ISSI  
512K x 8 (4-MBIT) DYNAMIC RAM  
WITH EDO PAGE MODE  
PRELIMINARY INFORMATION  
SEPTEMBER 2001  
FEATURES  
DESCRIPTION  
• TTL compatible inputs and outputs  
• Refresh Interval: 1024 cycles/16 ms  
The ISSI IS41C85120 and IS41LV85120 are 524,288 x 8-bit  
high-performance CMOS Dynamic Random Access  
Memory. Both products offer accelerated cycle access EDO  
Page Mode. EDO Page Mode allows 512 random accesses  
within a single row with access cycle time as short as 10ns per  
8-bit word. The Byte Write control, of upper and lower byte,  
makes the IS41C85120 and IS41LV85120 ideal for use in 16  
and 32-bit wide data bus systems.  
• Refresh Mode : RAS-Only, CAS-before-RAS  
(CBR), and Hidden  
• JEDEC standard pinout  
• Single power supply  
5V ± 10% (IS41C85120)  
3.3V ± 10% (IS41LV85120)  
• Industrail Temperature Range -40oC to 85oC  
These features make the IS41C85120 and IS41LV85120  
ideally suited for high band-width graphics, digital signal  
processing, high-performance computing systems, and pe-  
ripheral applications.  
The IS41C85120 and IS41LV85120 are available in a  
28-pin, 400-mil SOJ package.  
KEY TIMING PARAMETERS  
PIN CONFIGURATION  
28-Pin SOJ  
Parameter  
-35  
35  
10  
18  
12  
60  
-60  
60  
Unit  
ns  
Max. RAS Access Time (tRAC)  
Max. CAS Access Time (tCAC)  
Max. Column Address Access Time (tAA)  
Min. Fast Page Mode Cycle Time (tPC)  
Min. Read/Write Cycle Time (tRC)  
15  
ns  
30  
ns  
VCC  
I/O0  
I/O1  
I/O2  
I/O3  
NC  
1
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
GND  
I/O7  
I/O6  
I/O5  
I/O4  
CAS  
OE  
25  
ns  
2
110  
ns  
3
4
5
6
PIN DESCRIPTIONS  
WE  
RAS  
A9  
7
A0-A9  
I/O0-I/O7  
WE  
Address Inputs  
8
NC  
Data Inputs/Outputs  
Write Enable  
9
A8  
A0  
10  
11  
12  
13  
14  
A7  
A1  
A6  
OE  
Output Enable  
Row Address Strobe  
Column Address Strobe  
Power  
A2  
A5  
RAS  
CAS  
VCC  
A3  
A4  
VCC  
GND  
GND  
NC  
Ground  
No Connection  
This document contains PRELIMINARY INFORMATION data. ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the  
best possible product. We assume no responsibility for any errors which may appear in this publication. © Copyright 2001, Integrated Silicon Solution, Inc.  
Integrated Silicon Solution, Inc. — 1-800-379-4774  
PRELIMINARYINFORMATION Rev. 00B  
1
09/25/01  

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