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IS41C85125 PDF预览

IS41C85125

更新时间: 2024-01-17 19:47:04
品牌 Logo 应用领域
美国芯成 - ISSI /
页数 文件大小 规格书
16页 144K
描述
512K x 8 (4-MBIT) DYNAMIC RAM WITH FAST PAGE MODE

IS41C85125 数据手册

 浏览型号IS41C85125的Datasheet PDF文件第2页浏览型号IS41C85125的Datasheet PDF文件第3页浏览型号IS41C85125的Datasheet PDF文件第4页浏览型号IS41C85125的Datasheet PDF文件第5页浏览型号IS41C85125的Datasheet PDF文件第6页浏览型号IS41C85125的Datasheet PDF文件第7页 
®
IS41C85125  
IS41LV85125  
512K x 8 (4-MBIT) DYNAMIC RAM  
WITH FAST PAGE MODE  
ISSI  
PRELIMINARYINFORMATION  
AUGUST2001  
FEATURES  
DESCRIPTION  
The ISSI IS41Cꢁ5125 and IS41LVꢁ5125 are 512,2ꢁꢁ x ꢁ-bit  
high-performance CMOS Dynamic Random Access  
Memories.FastPageModeallows1024randomaccesses  
within a single row with access cycle time as short as 12  
ns per ꢁ-bit word.  
• Fast access and cycle time  
• TTL compatible inputs and outputs  
• Refresh Interval: 1024 cycles/16 ms  
Refresh Mode: RAS-Only, CAS-before-RAS  
(CBR), and Hidden  
ThesefeaturesmaketheIS41Cꢁ5125andtheIS41LVꢁ5125  
ideally suited for high band-width graphics, digital signal  
processing, high-performance computing systems, and  
peripheral applications.  
• JEDEC standard pinout  
• Single power supply:  
-- 5V 10ꢀ (IS41Cꢁ5125)  
-- 3.3V 10ꢀ (IS41LVꢁ5125)  
The IS41Cꢁ5125 and IS41LVꢁ5125 are available in a  
2ꢁ-pin, 400-mil SOJ package.  
• Industrialtemperatureavailable  
KEY TIMING PARAMETERS  
PIN CONFIGURATION  
28-Pin SOJ  
Parameter  
-35  
-60  
60  
Unit  
ns  
Max. RAS Access Time (tRAC)  
Max. CAS Access Time (tCAC)  
Max. Column Address Access Time (tAA)  
Min. Fast Page Mode Cycle Time (tPC)  
Min. Read/Write Cycle Time (tRC)  
35  
10  
1ꢁ  
12  
60  
15  
ns  
30  
ns  
VCC  
I/O0  
I/O1  
I/O2  
I/O3  
NC  
1
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
GND  
I/O7  
I/O6  
I/O5  
I/O4  
CAS  
OE  
25  
ns  
2
110  
ns  
3
4
5
6
PIN DESCRIPTIONS  
WE  
RAS  
A9  
7
A0-A9  
I/O0-I/O7  
WE  
Address Inputs  
8
NC  
Data Inputs/Outputs  
Write Enable  
9
A8  
A0  
10  
11  
12  
13  
14  
A7  
A1  
A6  
OE  
Output Enable  
Row Address Strobe  
Column Address Strobe  
Power  
A2  
A5  
RAS  
CAS  
VCC  
A3  
A4  
VCC  
GND  
GND  
NC  
Ground  
No Connection  
This document contains PRELIMINARY INFORMATION data. ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the  
best possible product. We assume no responsibility for any errors which may appear in this publication. © Copyright 2001, Integrated Silicon Solution, Inc.  
Integrated Silicon Solution, Inc. — 1-800-379-4774  
1
PRELIMINARYINFORMATION Rev. 00A  
09/25/01  

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