IDT71V632S6PFI8

更新时间： 2024-09-18 02:55:19

品牌	Logo	应用领域
艾迪悌 - IDT		计数器静态存储器
页数	文件大小	规格书
19页	274K
描述
64K x 32 3.3V Synchronous SRAM Pipelined Outputs Burst Counter, Single Cycle Deselect

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数据手册

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IDT71V632S6PFI8 数据手册

64K x 32

3.3VSynchronousSRAM

PipelinedOutputs

IDT71V632

BurstCounter,SingleCycleDeselect

Features

withfullsupportofthePentium™andPowerPC™processorinterfaces.

Thepipelinedburstarchitectureprovidescost-effective3-1-1-1second-

arycache performance forprocessors upto117MHz.

The IDT71V632 SRAM contains write, data, address, and control

registers.Internallogicallows theSRAMtogenerateaself-timedwrite

baseduponadecisionwhichcanbeleftuntiltheextremeendofthewrite

cycle.

Theburstmodefeatureoffersthehighestlevelofperformancetothe

systemdesigner, as the IDT71V632canprovide fourcycles ofdata for

asingleaddresspresentedtotheSRAM.Aninternalburstaddresscounter

acceptsthefirstcycleaddressfromtheprocessor,initiatingtheaccess

sequence.Thefirstcycleofoutputdatawillbepipelinedforonecyclebefore

it is available on the next rising clock edge. If burst mode operation is

selected(ADV=LOW),thesubsequentthreecyclesofoutputdatawillbe

availabletotheuseronthenextthreerisingclockedges.Theorderofthese

threeaddresseswillbedefinedbytheinternalburstcounterandtheLBO

inputpin.

◆

64K x 32 memory configuration

◆

Supports high system speed:

Commercial:

– A4 4.5ns clockaccess time (117MHz)

CommercialandIndustrial:

– 5 5ns clockaccess time (100MHz)

– 6 6ns clockaccess time (83MHz)

– 7 7ns clockaccess time (66MHz)

◆

Single-cycle deselect functionality (Compatible with

Micron Part # MT58LC64K32D7LG-XX)

LBO input selects interleaved or linear burst mode

Self-timed write cycle with global write control (GW), byte

◆

write enable (BWE), and byte writes (BWx)

Power down controlled by ZZ input

Operates with a single 3.3V power supply (+10/-5%)

Packaged in a JEDEC Standard 100-pin rectangular plastic

◆

thin quad flatpack (TQFP).

TheIDT71V632SRAMutilizesIDT'shigh-performance,high-volume

3.3V CMOS process, and is packaged in a JEDEC Standard 14mm x

20mm100-pinthinplasticquadflatpack(TQFP)foroptimumboarddensity

inbothdesktopandnotebookapplications.

Description

TheIDT71V632isa3.3Vhigh-speedSRAMorganizedas64Kx32

PinDescriptionSummary

A –A

Address Inputs

Input

I/O

Synchronous

Asynchronous

Synchronous

N/A

Chip Enable

CS , CS

Chips Selects

Output Enable

Global Write Enable

Byte Write Enable

Individual Byte Write Selects

Clock

BWE

BW BW BW BW

CLK

Burst Address Advance

Address Status (Cache Controller)

Address Status (Processor)

Linear / Interleaved Burst Order

Sleep Mode

Synchronous

ADV

ADSC

ADSP

LBO

Asynchronous

Synchronous

N/A

I/O⁰–I/O³¹

Data Input/Output

DD DDQ

V , V

3.3V

Power

SS SSQ

V , V

Array Ground, I/O Ground

N/A

3619 tbl 01

PentiumprocessorisatrademarkofIntelCorp.

PowerPCisatrademarkofInternationalBusinessMachines,Inc.

AUGUST 2001

DSC-3619/04

12 3 4 5 6 7...19

中文翻译

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与IDT71V632S6PFI8相关器件

型号	品牌	获取价格	描述	数据表
IDT71V632S75PF	ETC	获取价格	x32 Fast Synchronous SRAM
IDT71V632S7PF	IDT	获取价格	64K x 32 3.3V Synchronous SRAM Pipelined Outputs Burst Counter, Single Cycle Deselect
IDT71V632S7PF8	IDT	获取价格	64K x 32 3.3V Synchronous SRAM Pipelined Outputs Burst Counter, Single Cycle Deselect
IDT71V632S7PF9	IDT	获取价格	Cache SRAM, 64KX32, 7ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
IDT71V632S7PFG	IDT	获取价格	64K x 32 3.3V Synchronous SRAM Pipelined Outputs Burst Counter, Single Cycle Deselect
IDT71V632S7PFG8	IDT	获取价格	Cache SRAM, 64KX32, 7ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
IDT71V632S7PFGI	IDT	获取价格	Cache SRAM, 64KX32, 7ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
IDT71V632S7PFI	IDT	获取价格	64K x 32 3.3V Synchronous SRAM Pipelined Outputs Burst Counter, Single Cycle Deselect
IDT71V632S7PFI8	IDT	获取价格	64K x 32 3.3V Synchronous SRAM Pipelined Outputs Burst Counter, Single Cycle Deselect
IDT71V632S8PF	IDT	获取价格	64K x 32 3.3V Synchronous SRAM Pipelined Outputs Burst Counter, Single Cycle Deselect

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