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IDT71V632S8PF8

更新时间： 2024-09-17 23:15:47
品牌 Logo 应用领域
艾迪悌 - IDT 计数器静态存储器
页数 文件大小 规格书
19页 274K
描述
64K x 32 3.3V Synchronous SRAM Pipelined Outputs Burst Counter, Single Cycle Deselect

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IDT71V632S8PF8 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
包装说明：TQFP-100Reach Compliance Code：not_compliant
风险等级：5.92最长访问时间：8 ns
最大时钟频率 (fCLK)：60 MHzI/O 类型：COMMON
JESD-30 代码：R-PQFP-G100JESD-609代码：e0
内存密度：2097152 bit内存集成电路类型：STANDARD SRAM
内存宽度：32湿度敏感等级：3
端子数量：100字数：65536 words
字数代码：64000工作模式：SYNCHRONOUS
最高工作温度：70 °C最低工作温度：
组织：64KX32输出特性：3-STATE
封装主体材料：PLASTIC/EPOXY封装代码：QFP
封装等效代码：QFP100,.63X.87封装形状：RECTANGULAR
封装形式：FLATPACK并行/串行：PARALLEL
电源：3.3 V认证状态：Not Qualified
最大待机电流：0.009 A最小待机电流：3.14 V
子类别：SRAMs最大压摆率：0.24 mA
标称供电电压 (Vsup)：3.3 V表面贴装：YES
技术：CMOS温度等级：COMMERCIAL
端子面层：Tin/Lead (Sn85Pb15)端子形式：GULL WING
端子节距：0.635 mm端子位置：QUAD
Base Number Matches：1

IDT71V632S8PF8 数据手册

 浏览型号IDT71V632S8PF8的Datasheet PDF文件第2页浏览型号IDT71V632S8PF8的Datasheet PDF文件第3页浏览型号IDT71V632S8PF8的Datasheet PDF文件第4页浏览型号IDT71V632S8PF8的Datasheet PDF文件第5页浏览型号IDT71V632S8PF8的Datasheet PDF文件第6页浏览型号IDT71V632S8PF8的Datasheet PDF文件第7页 
64K x 32  
3.3VSynchronousSRAM  
PipelinedOutputs  
IDT71V632  
BurstCounter,SingleCycleDeselect  
Features  
withfullsupportofthePentium™andPowerPC™processorinterfaces.  
Thepipelinedburstarchitectureprovidescost-effective3-1-1-1second-  
arycache performance forprocessors upto117MHz.  
The IDT71V632 SRAM contains write, data, address, and control  
registers.Internallogicallows theSRAMtogenerateaself-timedwrite  
baseduponadecisionwhichcanbeleftuntiltheextremeendofthewrite  
cycle.  
Theburstmodefeatureoffersthehighestlevelofperformancetothe  
systemdesigner, as the IDT71V632canprovide fourcycles ofdata for  
asingleaddresspresentedtotheSRAM.Aninternalburstaddresscounter  
acceptsthefirstcycleaddressfromtheprocessor,initiatingtheaccess  
sequence.Thefirstcycleofoutputdatawillbepipelinedforonecyclebefore  
it is available on the next rising clock edge. If burst mode operation is  
selected(ADV=LOW),thesubsequentthreecyclesofoutputdatawillbe  
availabletotheuseronthenextthreerisingclockedges.Theorderofthese  
threeaddresseswillbedefinedbytheinternalburstcounterandtheLBO  
inputpin.  
◆
64K x 32 memory configuration  
◆
Supports high system speed:  
Commercial:  
– A4 4.5ns clockaccess time (117MHz)  
CommercialandIndustrial:  
– 5 5ns clockaccess time (100MHz)  
– 6 6ns clockaccess time (83MHz)  
– 7 7ns clockaccess time (66MHz)  
◆
Single-cycle deselect functionality (Compatible with  
Micron Part # MT58LC64K32D7LG-XX)  
LBO input selects interleaved or linear burst mode  
Self-timed write cycle with global write control (GW), byte  
◆
◆
write enable (BWE), and byte writes (BWx)  
Power down controlled by ZZ input  
Operates with a single 3.3V power supply (+10/-5%)  
Packaged in a JEDEC Standard 100-pin rectangular plastic  
◆
◆
◆
thin quad flatpack (TQFP).  
TheIDT71V632SRAMutilizesIDT'shigh-performance,high-volume  
3.3V CMOS process, and is packaged in a JEDEC Standard 14mm x  
20mm100-pinthinplasticquadflatpack(TQFP)foroptimumboarddensity  
inbothdesktopandnotebookapplications.  
Description  
TheIDT71V632isa3.3Vhigh-speedSRAMorganizedas64Kx32  
PinDescriptionSummary  
0
15  
A –A  
Address Inputs  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
I/O  
Synchronous  
Synchronous  
Synchronous  
Asynchronous  
Synchronous  
Synchronous  
Synchronous  
N/A  
Chip Enable  
CE  
0
1
CS , CS  
Chips Selects  
Output Enable  
OE  
Global Write Enable  
Byte Write Enable  
Individual Byte Write Selects  
Clock  
GW  
BWE  
1,  
2,  
3,  
4
BW BW BW BW  
CLK  
Burst Address Advance  
Address Status (Cache Controller)  
Address Status (Processor)  
Linear / Interleaved Burst Order  
Sleep Mode  
Synchronous  
Synchronous  
Synchronous  
DC  
ADV  
ADSC  
ADSP  
LBO  
ZZ  
Asynchronous  
Synchronous  
N/A  
I/O0–I/O31  
Data Input/Output  
DD DDQ  
V , V  
3.3V  
Power  
Power  
SS SSQ  
V , V  
Array Ground, I/O Ground  
N/A  
3619 tbl 01  
PentiumprocessorisatrademarkofIntelCorp.  
PowerPCisatrademarkofInternationalBusinessMachines,Inc.  
AUGUST 2001  
1
©2000IntegratedDeviceTechnology,Inc.  
DSC-3619/04  
1234567...19

中文翻译

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 		64K x 32 3.3V Synchronous SRAM Flow-Through Outputs Burst Counter, Single Cycle Deselect
IDT71V633S11PF8 IDT

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 		Cache SRAM, 64KX32, 11ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, 1 MM PITCH, PLASTIC,
IDT71V633S11PFI IDT

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 		64K x 32 3.3V Synchronous SRAM Flow-Through Outputs Burst Counter, Single Cycle Deselect
IDT71V633S12PF IDT

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