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IDT71V633S12PF PDF预览

IDT71V633S12PF

更新时间: 2024-11-22 22:10:35
品牌 Logo 应用领域
艾迪悌 - IDT 计数器静态存储器
页数 文件大小 规格书
19页 270K
描述
64K x 32 3.3V Synchronous SRAM Flow-Through Outputs Burst Counter, Single Cycle Deselect

IDT71V633S12PF 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:QFP包装说明:14 X 20 MM, 1.40 MM HEIGHT, 1 MM PITCH, PLASTIC, MO-135DJ, TQFP-100
针数:100Reach Compliance Code:not_compliant
ECCN代码:3A991.B.2.AHTS代码:8542.32.00.41
风险等级:5.83最长访问时间:12 ns
最大时钟频率 (fCLK):50 MHzI/O 类型:COMMON
JESD-30 代码:R-PQFP-G100JESD-609代码:e0
长度:20 mm内存密度:2097152 bit
内存集成电路类型:CACHE SRAM内存宽度:32
湿度敏感等级:3功能数量:1
端口数量:1端子数量:100
字数:65536 words字数代码:64000
工作模式:SYNCHRONOUS最高工作温度:70 °C
最低工作温度:组织:64KX32
输出特性:3-STATE可输出:YES
封装主体材料:PLASTIC/EPOXY封装代码:LQFP
封装等效代码:QFP100,.63X.87封装形状:RECTANGULAR
封装形式:FLATPACK, LOW PROFILE并行/串行:PARALLEL
峰值回流温度(摄氏度):240电源:3.3 V
认证状态:Not Qualified座面最大高度:1.6 mm
最大待机电流:0.015 A最小待机电流:3.14 V
子类别:SRAMs最大压摆率:0.15 mA
最大供电电压 (Vsup):3.63 V最小供电电压 (Vsup):3.135 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:Tin/Lead (Sn85Pb15)端子形式:GULL WING
端子节距:0.65 mm端子位置:QUAD
处于峰值回流温度下的最长时间:20宽度:14 mm

IDT71V633S12PF 数据手册

 浏览型号IDT71V633S12PF的Datasheet PDF文件第2页浏览型号IDT71V633S12PF的Datasheet PDF文件第3页浏览型号IDT71V633S12PF的Datasheet PDF文件第4页浏览型号IDT71V633S12PF的Datasheet PDF文件第5页浏览型号IDT71V633S12PF的Datasheet PDF文件第6页浏览型号IDT71V633S12PF的Datasheet PDF文件第7页 
IDT71V633  
64K x 32  
3.3VSynchronousSRAM  
Flow-ThroughOutputs  
BurstCounter,SingleCycleDeselect  
Features  
64K x 32 memory configuration  
tectureprovidescost-effective2-1-1-1performanceforprocessorsupto  
50 MHz.  
Supports high performance system speed  
Commercial:  
— 11 11ns Clock-to-Data Access (50 MHz)  
CommercialandIndustrial:  
— 12 12ns Clock-to-Data Access (50 MHz)  
Single-cycle deselect functionality (Compatible with  
TheIDT71V633SRAMcontainswrite,data-input,addressandcontrol  
registers. There are no registers in the data output path (flow-through  
architecture).InternallogicallowstheSRAMtogenerateaself-timedwrite  
baseduponadecisionwhichcanbeleftuntiltheextremeendofthewrite  
cycle.  
Micron Part # MT58LC64K32B2LG-XX)  
LBO input selects interleaved or linear burst mode  
Self-timed write cycle with global write control (GW), byte  
write enable (BWE), and byte writes (BWx)  
Power down controlled by ZZ input  
Single 3.3V power supply (+10/-5%)  
Packaged in a JEDEC Standard 100-pin rectangular plastic  
thin quad flatpack (TQFP).  
Theburstmodefeatureoffersthehighestlevelofperformancetothe  
systemdesigner, as the IDT71V633canprovide fourcycles ofdata for  
a single address presented to the SRAM. An internal burst address  
counteracceptsthefirstcycleaddressfromtheprocessor,initiatingthe  
accesssequence.Thefirstcycleofoutputdatawillflow-throughfromthe  
arrayafteraclock-to-dataaccesstimedelayfromtherisingclockedgeof  
the same cycle. If burst mode operation is selected (ADV=LOW), the  
subsequentthreecyclesofoutputdatawillbeavailabletotheuseronthe  
nextthreerisingclockedges. Theorderofthesethreeaddresseswillbe  
definedbytheinternalburstcounterandtheLBOinputpin.  
TheIDT71V633SRAMutilizesIDT'shigh-performance3.3VCMOS  
process,andispackagedinaJEDECStandard14mmx20mm100-pin  
thinplasticquadflatpack(TQFP).  
Description  
TheIDT71V633is a3.3Vhigh-speed2,097,152-bit(2-Mbit)SRAM  
organizedas 64Kx32withfullsupportofvarious processorinterfaces  
includingthePentium™andPowerPC.Theflow-throughburstarchi-  
PinDescription  
0
15  
A –A  
Address Inputs  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
I/O  
Synchronous  
Synchronous  
Synchronous  
Asynchronous  
Synchronous  
Synchronous  
Synchronous  
N/A  
Chip Enable  
CE  
0
1
CS , CS  
Chips Selects  
Output Enable  
OE  
Global Write Enable  
Byte Write Enable  
GW  
BWE  
1
Individual Byte Write Selects  
Clock Input  
4
BW BW  
CLK  
Burst Address Advance  
Address Status (Cache Controller)  
Address Status (Processor)  
Linear / Interleaved Burst Order  
Sleep Mode  
Synchronous  
Synchronous  
Synchronous  
DC  
ADV  
ADSC  
ADSP  
LBO  
ZZ  
Asynchronous  
Synchronous  
N/A  
0
31  
I/O –I/O  
Data Input/Output  
DD DDQ  
V , V  
Core and I/O Power Supply (3.3V)  
Array Ground, I/O Ground  
Power  
Power  
SS SSQ  
V , V  
N/A  
3780 tbl 01  
PentiumisatrademarkofIntelCorp.  
PowerPCisatrademarkofInternationalBusinessMachines,Inc.  
AUGUST 2001  
1
DSC-3780/05  
©2000IntegratedDeviceTechnology,Inc.  

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