64K x 32
IDT71V632/Z
3.3VSynchronousSRAM
PipelinedOutputs
BurstCounter,SingleCycleDeselect
Features
withfullsupportofthePentium™andPowerPC™processorinterfaces.
Thepipelinedburstarchitectureprovidescost-effective3-1-1-1second-
arycache performance forprocessors upto117MHz.
The IDT71V632 SRAM contains write, data, address, and control
registers.Internallogicallows theSRAMtogenerateaself-timedwrite
baseduponadecisionwhichcanbeleftuntiltheextremeendofthewrite
cycle.
Theburstmodefeatureoffersthehighestlevelofperformancetothe
systemdesigner, as the IDT71V632canprovide fourcycles ofdata for
asingleaddresspresentedtotheSRAM.Aninternalburstaddresscounter
acceptsthefirstcycleaddressfromtheprocessor,initiatingtheaccess
sequence.Thefirstcycleofoutputdatawillbepipelinedforonecyclebefore
it is available on the next rising clock edge. If burst mode operation is
selected(ADV=LOW),thesubsequentthreecyclesofoutputdatawillbe
availabletotheuseronthenextthreerisingclockedges.Theorderofthese
threeaddresseswillbedefinedbytheinternalburstcounterandtheLBO
inputpin.
◆
64K x 32 memory configuration
◆
Supports high system speed:
Commercial:
– A4 4.5ns clockaccess time (117MHz)
CommercialandIndustrial:
– 5 5ns clockaccess time (100MHz)
– 6 6ns clockaccess time (83MHz)
– 7 7ns clockaccess time (66MHz)
◆
Single-cycle deselect functionality (Compatible with
Micron Part # MT58LC64K32D7LG-XX)
LBO input selects interleaved or linear burst mode
Self-timed write cycle with global write control (GW), byte
◆
◆
write enable (BWE), and byte writes (BWx)
Power down controlled by ZZ input
Operates with a single 3.3V power supply (+10/-5%)
Packaged in a JEDEC Standard 100-pin rectangular plastic
◆
◆
◆
thin quad flatpack (TQFP).
TheIDT71V632SRAMutilizesIDT'shigh-performance,high-volume
3.3V CMOS process, and is packaged in a JEDEC Standard 14mm x
20mm100-pinthinplasticquadflatpack(TQFP)foroptimumboarddensity
inbothdesktopandnotebookapplications.
Description
TheIDT71V632isa3.3Vhigh-speedSRAMorganizedas64Kx32
PinDescriptionSummary
A0–A15
Address Inputs
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
I/O
Synchronous
Synchronous
Synchronous
Asynchronous
Synchronous
Synchronous
Synchronous
N/A
Chip Enable
CE
CS
0
, CS
1
Chips Selects
Output Enable
OE
GW
Global Write Enable
Byte Write Enable
Individual Byte Write Selects
Clock
BWE
BW1, BW2, BW3, BW
4
CLK
ADV
ADSC
ADSP
LBO
Burst Address Advance
Address Status (Cache Controller)
Address Status (Processor)
Linear / Interleaved Burst Order
Sleep Mode
Synchronous
Synchronous
Synchronous
DC
ZZ
Asynchronous
Synchronous
N/A
I/O
0
–I/O31
DD, VDDQ
SS, VSSQ
Data Input/Output
V
3.3V
Power
Power
V
Array Ground, I/O Ground
N/A
3619 tbl 01
PentiumprocessorisatrademarkofIntelCorp.
PowerPCisatrademarkofInternationalBusinessMachines,Inc.
OCTOBER 2008
1
©2007IntegratedDeviceTechnology,Inc.
DSC-3619/05