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IDT71V632S7PFGI PDF预览

IDT71V632S7PFGI

更新时间: 2024-11-26 12:58:35
品牌 Logo 应用领域
艾迪悌 - IDT 计数器静态存储器
页数 文件大小 规格书
19页 274K
描述
Cache SRAM, 64KX32, 7ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100

IDT71V632S7PFGI 技术参数

是否无铅:不含铅是否Rohs认证:符合
生命周期:Active零件包装代码:QFP
包装说明:LQFP, QFP100,.63X.87针数:100
Reach Compliance Code:compliantECCN代码:3A991.B.2.A
HTS代码:8542.32.00.41风险等级:5.24
Is Samacsys:N最长访问时间:7 ns
其他特性:ALSO REQUIRES 3.3V I/O SUPPLY最大时钟频率 (fCLK):66 MHz
I/O 类型:COMMONJESD-30 代码:R-PQFP-G100
JESD-609代码:e3长度:20 mm
内存密度:2097152 bit内存集成电路类型:CACHE SRAM
内存宽度:32湿度敏感等级:3
功能数量:1端子数量:100
字数:65536 words字数代码:64000
工作模式:SYNCHRONOUS最高工作温度:85 °C
最低工作温度:-40 °C组织:64KX32
输出特性:3-STATE封装主体材料:PLASTIC/EPOXY
封装代码:LQFP封装等效代码:QFP100,.63X.87
封装形状:RECTANGULAR封装形式:FLATPACK, LOW PROFILE
并行/串行:PARALLEL峰值回流温度(摄氏度):260
电源:3.3 V认证状态:Not Qualified
座面最大高度:1.6 mm最大待机电流:0.015 A
最小待机电流:3.14 V子类别:SRAMs
最大压摆率:0.16 mA最大供电电压 (Vsup):3.63 V
最小供电电压 (Vsup):3.135 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Matte Tin (Sn) - annealed
端子形式:GULL WING端子节距:0.65 mm
端子位置:QUAD处于峰值回流温度下的最长时间:30
宽度:14 mmBase Number Matches:1

IDT71V632S7PFGI 数据手册

 浏览型号IDT71V632S7PFGI的Datasheet PDF文件第2页浏览型号IDT71V632S7PFGI的Datasheet PDF文件第3页浏览型号IDT71V632S7PFGI的Datasheet PDF文件第4页浏览型号IDT71V632S7PFGI的Datasheet PDF文件第5页浏览型号IDT71V632S7PFGI的Datasheet PDF文件第6页浏览型号IDT71V632S7PFGI的Datasheet PDF文件第7页 
64K x 32  
3.3VSynchronousSRAM  
PipelinedOutputs  
IDT71V632  
BurstCounter,SingleCycleDeselect  
Features  
withfullsupportofthePentium™andPowerPC™processorinterfaces.  
Thepipelinedburstarchitectureprovidescost-effective3-1-1-1second-  
arycache performance forprocessors upto117MHz.  
The IDT71V632 SRAM contains write, data, address, and control  
registers.Internallogicallows theSRAMtogenerateaself-timedwrite  
baseduponadecisionwhichcanbeleftuntiltheextremeendofthewrite  
cycle.  
Theburstmodefeatureoffersthehighestlevelofperformancetothe  
systemdesigner, as the IDT71V632canprovide fourcycles ofdata for  
asingleaddresspresentedtotheSRAM.Aninternalburstaddresscounter  
acceptsthefirstcycleaddressfromtheprocessor,initiatingtheaccess  
sequence.Thefirstcycleofoutputdatawillbepipelinedforonecyclebefore  
it is available on the next rising clock edge. If burst mode operation is  
selected(ADV=LOW),thesubsequentthreecyclesofoutputdatawillbe  
availabletotheuseronthenextthreerisingclockedges.Theorderofthese  
threeaddresseswillbedefinedbytheinternalburstcounterandtheLBO  
inputpin.  
64K x 32 memory configuration  
Supports high system speed:  
Commercial:  
A4 4.5ns clockaccess time (117MHz)  
CommercialandIndustrial:  
– 5 5ns clockaccess time (100MHz)  
– 6 6ns clockaccess time (83MHz)  
– 7 7ns clockaccess time (66MHz)  
Single-cycle deselect functionality (Compatible with  
Micron Part # MT58LC64K32D7LG-XX)  
LBO input selects interleaved or linear burst mode  
Self-timed write cycle with global write control (GW), byte  
write enable (BWE), and byte writes (BWx)  
Power down controlled by ZZ input  
Operates with a single 3.3V power supply (+10/-5%)  
Packaged in a JEDEC Standard 100-pin rectangular plastic  
thin quad flatpack (TQFP).  
TheIDT71V632SRAMutilizesIDT'shigh-performance,high-volume  
3.3V CMOS process, and is packaged in a JEDEC Standard 14mm x  
20mm100-pinthinplasticquadflatpack(TQFP)foroptimumboarddensity  
inbothdesktopandnotebookapplications.  
Description  
TheIDT71V632isa3.3Vhigh-speedSRAMorganizedas64Kx32  
PinDescriptionSummary  
0
15  
A –A  
Address Inputs  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
I/O  
Synchronous  
Synchronous  
Synchronous  
Asynchronous  
Synchronous  
Synchronous  
Synchronous  
N/A  
Chip Enable  
CE  
0
1
CS , CS  
Chips Selects  
Output Enable  
OE  
Global Write Enable  
Byte Write Enable  
Individual Byte Write Selects  
Clock  
GW  
BWE  
1,  
2,  
3,  
4
BW BW BW BW  
CLK  
Burst Address Advance  
Address Status (Cache Controller)  
Address Status (Processor)  
Linear / Interleaved Burst Order  
Sleep Mode  
Synchronous  
Synchronous  
Synchronous  
DC  
ADV  
ADSC  
ADSP  
LBO  
ZZ  
Asynchronous  
Synchronous  
N/A  
I/O0–I/O31  
Data Input/Output  
DD DDQ  
V , V  
3.3V  
Power  
Power  
SS SSQ  
V , V  
Array Ground, I/O Ground  
N/A  
3619 tbl 01  
PentiumprocessorisatrademarkofIntelCorp.  
PowerPCisatrademarkofInternationalBusinessMachines,Inc.  
AUGUST 2001  
1
©2000IntegratedDeviceTechnology,Inc.  
DSC-3619/04  

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