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IDT5T93GL161PFGI8

更新时间： 2024-11-03 09:18:43
品牌 Logo 应用领域
艾迪悌 - IDT /
页数 文件大小 规格书
20页 871K
描述
Low Skew Clock Driver, 5T Series, 16 True Output(s), 0 Inverted Output(s), CMOS, PQFP64, GREEN, TQFP-64

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IDT5T93GL161PFGI8 数据手册

 浏览型号IDT5T93GL161PFGI8的Datasheet PDF文件第2页浏览型号IDT5T93GL161PFGI8的Datasheet PDF文件第3页浏览型号IDT5T93GL161PFGI8的Datasheet PDF文件第4页浏览型号IDT5T93GL161PFGI8的Datasheet PDF文件第5页浏览型号IDT5T93GL161PFGI8的Datasheet PDF文件第6页浏览型号IDT5T93GL161PFGI8的Datasheet PDF文件第7页 
2.5V LVDS, 1:16 GLITCHLESS CLOCK BUFFER  
TERABUFFER™ II  
IDT5T93GL161  
General Description  
Features  
The IDT5T93GL161 2.5V differential clock buffer is a  
• Guaranteed low skew: <75ps (maximum)  
user-selectable differential input to sixteen LVDS outputs. The  
fanout from a differential input to sixteen LVDS outputs reduces  
loading on the preceding driver and provides an efficient clock  
distribution network. The IDT5T93GL161 can act as a translator  
from a differential HSTL, eHSTL, LVEPECL (2.5V), LVPECL  
(3.3V), CML, or LVDS input to LVDS outputs. A single-ended 3.3V  
/ 2.5V LVTTL input can also be used to translate to LVDS outputs.  
The redundant input capability allows for a glitchless change-over  
from a primary clock source to a secondary clock source.  
Selectable inputs are controlled by SEL. During the switchover,  
the output will disable LOW for up to three clock cycles of the  
previously-selected input clock. The outputs will remain LOW for  
up to three clock cycles of the newly-selected clock, after which  
the outputs will start from the newly-selected input. A FSEL pin  
has been implemented to control the switchover in cases where a  
clock source is absent or is driven to DC levels below the minimum  
specifications.  
• Very low duty cycle distortion: <100ps (maximum)  
• High speed propagation delay: <2.2ns (maximum)  
• Up to 450MHz operation  
• Selectable inputs  
• Hot insertable and over-voltage tolerant inputs  
• 3.3V/2.5V LVTTL, HSTL, eHSTL, LVEPECL (2.5V), LVPECL  
(3.3V), CML or LVDS input interface  
• Selectable differential inputs to sixteen LVDS outputs  
• Power-down mode  
• At power-up, FSEL should be LOW  
• 2.5V VDD  
• -40°C to 85°C ambient operating temperature  
• Available in TQFP package  
The IDT5T93GL161 outputs can be asynchronously  
enabled/disabled. When disabled, the outputs will drive to the  
value selected by the GL pin. Multiple power and grounds reduce  
noise.  
Applications  
Pin Assignment  
• Clock distribution  
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49  
1
2
3
4
5
6
7
8
9
G1  
GND  
GND  
48  
47  
46  
G2  
GND  
GND  
VDD  
VDD  
45  
44  
43  
Q1  
Q1  
Q12  
Q12  
Q11  
Q11  
Q10  
IDT5T93GL161  
64-Lead TQFP E-Pad  
10mm x 10mm x 1.0mm package body  
Y package  
Q2  
Q2  
Q3  
42  
41  
40  
Q3  
Q4  
Q4  
10  
11  
12  
Q10  
Q9  
39  
38  
37  
Top View  
Q9  
V
DD  
13  
V
DD  
36  
35  
34  
A1 14  
A1  
GND 16  
17 18 19 20 21  
A2  
A2  
15  
GND  
33  
23 24 25 26 27 28 29 30 31 32  
22  
IDT™ LVDS GLITCHLESS CLOCK BUFFER TERABUFFER™ II  
1
IDT5T93GL161 REV. A SEPTEMBER 12, 2008  
1234567...20

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 		PRECISION CLOCK GENERATOR OC-192 APPLICATIONS
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 		PLL Based Clock Driver, 5T Series, 2 True Output(s), 0 Inverted Output(s), PQCC28, PLASTIC
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 		PLL Based Clock Driver, 5T Series, 10 True Output(s), 0 Inverted Output(s), PQCC68, PLASTI

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