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IDT5T9890NLI8 PDF预览

IDT5T9890NLI8

更新时间: 2024-11-20 14:51:23
品牌 Logo 应用领域
艾迪悌 - IDT 驱动逻辑集成电路
页数 文件大小 规格书
36页 207K
描述
PLL Based Clock Driver, 5T Series, 10 True Output(s), 0 Inverted Output(s), PQCC68, PLASTIC, VFQFPN-68

IDT5T9890NLI8 技术参数

是否Rohs认证:不符合生命周期:Obsolete
零件包装代码:QFN包装说明:PLASTIC, VFQFPN-68
针数:68Reach Compliance Code:not_compliant
HTS代码:8542.39.00.01风险等级:5.88
Is Samacsys:N系列:5T
输入调节:SCHMITT TRIGGER MUXJESD-30 代码:S-PQCC-N68
JESD-609代码:e0长度:10 mm
逻辑集成电路类型:PLL BASED CLOCK DRIVER最大I(ol):0.012 A
湿度敏感等级:3功能数量:1
反相输出次数:端子数量:68
实输出次数:10最高工作温度:85 °C
最低工作温度:-40 °C输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:VQCCN
封装等效代码:LCC68,.4SQ,20封装形状:SQUARE
封装形式:CHIP CARRIER, VERY THIN PROFILE峰值回流温度(摄氏度):NOT SPECIFIED
电源:1.5/2.5,2.5 V认证状态:Not Qualified
Same Edge Skew-Max(tskwd):0.1 ns座面最大高度:1 mm
子类别:Clock Drivers最大供电电压 (Vsup):2.7 V
最小供电电压 (Vsup):2.3 V标称供电电压 (Vsup):2.5 V
表面贴装:YES温度等级:INDUSTRIAL
端子面层:Tin/Lead (Sn85Pb15)端子形式:NO LEAD
端子节距:0.5 mm端子位置:QUAD
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:10 mm
最小 fmax:250 MHzBase Number Matches:1

IDT5T9890NLI8 数据手册

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IDT5T9890  
EEPROM PROGRAMMABLE 2.5V  
PROGRAMMABLE SKEW PLL  
CLOCK DRIVER  
FEATURES:  
DESCRIPTION:  
• 2.5VDD  
The IDT5T9890 is a 2.5V PLL clock driver intended for high perfor-  
mancecomputinganddata-communicationsapplications.Akeyfeatureof  
theprogrammableskewistheabilityofoutputstoleadorlagtheREFinput  
signal. TheIDT5T9890hastenprogrammableskewoutputsinfivebanks  
of two, plus a dedicated differential feedback. Skew is controlled through  
theuseof JTAGorI2Cprogramming. Theredundantinputcapabilityallows  
for a smooth change over to a secondary clock source when the primary  
clock source is absent.  
• 5 pairs of programmable skew outputs  
• Low skew: 100ps all outputs at same interface level, 250ps all  
outputs at different interface levels  
• Selectable positive or negative edge synchronization  
• Tolerant of spread spectrum input clock  
• Synchronous output enable  
• Selectable inputs  
TheclockdrivercanbeconfiguredthroughtheuseofJTAG/I2Cprogram-  
ming. An internal EEPROM will allow the user to save and restore the  
configurationofthedevice.  
• Input frequency: 4.17MHz to 250MHz  
• Output frequency: 12.5MHz to 250MHz  
• Internal non-volatile EEPROM  
• JTAG or I2C bus serial interface for programming  
• Hot insertable and over-voltage tolerant inputs  
• Feedback divide selection with multiply ratios of (1-6, 8, 10, 12)  
• Selectable HSTL, eHSTL, 1.8V/2.5V LVTTL, or LVEPECL input  
interface  
• Selectable HSTL, eHSTL, or 1.8V/2.5V LVTTL output interface for  
each output bank  
• Selectable differential or single-ended inputs and ten single-  
ended outputs  
The feedback bank allows divide-by-functionality from 1 to 12 through  
theuseof JTAGorI2Cprogramming. Thisprovidestheuserwithfrequency  
multiplication1to12withoutusingdividedoutputsforfeedback. Eachoutput  
bank also allows for a divide-by-functionality of 2 or 4.  
The IDT5T9890 features a user-selectable, single-ended or differential  
inputtotensingle-endedoutputs. Theclockdriveralsoactsasatranslatorfrom  
a differential HSTL, eHSTL, 1.8V/2.5V LVTTL, LVEPECL, or single-ended  
1.8V/2.5VLVTTLinputtoHSTL,eHSTL,or1.8V/2.5VLVTTLoutputs. Each  
output bank can be individually configured to be either HSTL, eHSTL, 2.5V  
LVTTL,or1.8VLVTTL,includingthefeedbackbank. Also,eachclockinput  
can be individually configured to accept 2.5V LVTTL, 1.8V LVTTL, or  
differentialsignals. Theoutputscanbesynchronouslyenabled/disabled.  
Furthermore, alltheoutputscanbesynchronizedwiththepositiveedge  
of the REF clock input or the negative edge of REF.  
• PLL bypass for DC testing  
• External differential feedback, internal loop filter  
• Low Jitter: <75ps cycle-to-cycle, all outputs at same interface  
level: <100ps cycle-to-cycle all outputs at different interface  
levels  
• Power-down mode  
• Lock indicator  
• Available in VFQFPN package  
TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.  
INDUSTRIAL TEMPERATURE RANGE  
JUNE 2004  
1
c
2004 Integrated Device Technology, Inc.  
DSC - 6504/13  

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