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IDT5T9950APFGI8 PDF预览

IDT5T9950APFGI8

更新时间: 2024-11-24 20:01:43
品牌 Logo 应用领域
艾迪悌 - IDT 驱动逻辑集成电路
页数 文件大小 规格书
9页 113K
描述
PLL Based Clock Driver, 5T Series, 8 True Output(s), 0 Inverted Output(s), PQFP32, LEAD FREE, TQFP-32

IDT5T9950APFGI8 技术参数

是否无铅:不含铅是否Rohs认证:符合
生命周期:Obsolete零件包装代码:QFP
包装说明:LEAD FREE, TQFP-32针数:32
Reach Compliance Code:compliantHTS代码:8542.39.00.01
风险等级:5.81Is Samacsys:N
系列:5T输入调节:STANDARD
JESD-30 代码:S-PQFP-G32JESD-609代码:e3
长度:7 mm逻辑集成电路类型:PLL BASED CLOCK DRIVER
湿度敏感等级:3功能数量:1
反相输出次数:端子数量:32
实输出次数:8最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:LQFP封装形状:SQUARE
封装形式:FLATPACK, LOW PROFILE峰值回流温度(摄氏度):260
认证状态:Not QualifiedSame Edge Skew-Max(tskwd):0.5 ns
座面最大高度:1.6 mm最大供电电压 (Vsup):2.7 V
最小供电电压 (Vsup):2.3 V标称供电电压 (Vsup):2.5 V
表面贴装:YES温度等级:INDUSTRIAL
端子面层:MATTE TIN端子形式:GULL WING
端子节距:0.8 mm端子位置:QUAD
处于峰值回流温度下的最长时间:30宽度:7 mm
最小 fmax:200 MHzBase Number Matches:1

IDT5T9950APFGI8 数据手册

 浏览型号IDT5T9950APFGI8的Datasheet PDF文件第2页浏览型号IDT5T9950APFGI8的Datasheet PDF文件第3页浏览型号IDT5T9950APFGI8的Datasheet PDF文件第4页浏览型号IDT5T9950APFGI8的Datasheet PDF文件第5页浏览型号IDT5T9950APFGI8的Datasheet PDF文件第6页浏览型号IDT5T9950APFGI8的Datasheet PDF文件第7页 
2.5V PROGRAMMABLE  
IDT5T9950/A  
SKEW PLL CLOCK DRIVER  
TURBOCLOCK™ II JR.  
FEATURES:  
DESCRIPTION:  
• Ref input is 3.3V tolerant  
The IDT5T9950is a highfanout2.5VPLLbasedclockdriverintended  
forhighperformancecomputinganddata-communicationsapplications.A  
keyfeatureoftheprogrammableskewistheabilityofoutputstoleadorlag  
the REF input signal. The IDT5T9950 has eight programmable skew  
outputs infourbanks of2.Skewis controlledby3-levelinputsignals that  
may be hard-wired to appropriate high-mid-low levels.  
• 4 pairs of programmable skew outputs  
Low skew: 185ps same pair, 250ps all outputs  
• Selectable positive or negative edge synchronization:  
Excellent for DSP applications  
• Synchronous output enable  
Input frequency:  
– Std: 6MHz to 160MHz  
A: 6MHz to 200MHz  
• Output frequency:  
WhenthesOEpinisheldlow,alltheoutputsaresynchronouslyenabled.  
However, if sOE is held high, all the outputs except 2Q0 and 2Q1 are  
synchronouslydisabled. TheLOCKoutputassertstoindicatewhenPhase  
Lock has been achieved.  
– Std: 6MHz to 160MHz  
A: 6MHz to 200MHz  
Furthermore,whenPEisheldhigh,alltheoutputsaresynchronizedwith  
thepositiveedgeoftheREFclockinput.WhenPEisheldlow,alltheoutputs  
are synchronized with the negative edge of REF. The IDT5T9950 has  
LVTTLoutputs with12mAbalanceddrive outputs.  
• 2x, 4x, 1/2, and 1/4 outputs  
• 3-level inputs for skew and PLL range control  
• PLL bypass for DC testing  
• External feedback, internal loop filter  
• 12mA balanced drive outputs  
Low Jitter: <100ps cycle-to-cycle  
• Standard and A speed grades  
Available in TQFP package  
FUNCTIONALBLOCKDIAGRAM  
sOE  
1Q0  
Skew  
Select  
1Q1  
3
3
1F1:0  
2F1:0  
PE TEST  
3
2Q0  
2Q1  
Skew  
Select  
3
3
3
3
REF  
PLL  
FB  
3Q0  
3Q1  
Skew  
Select  
3
3
FS  
3F1:0  
4F1:0  
4Q0  
4Q1  
Skew  
Select  
3
TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.  
INDUSTRIAL TEMPERATURE RANGE  
OCTOBER 2008  
1
c
2002 Integrated Device Technology, Inc.  
DSC 5869/6  

IDT5T9950APFGI8 替代型号

型号 品牌 替代类型 描述 数据表
IDT5T9950APFGI IDT

完全替代

PLL Based Clock Driver, 5T Series, 8 True Output(s), 0 Inverted Output(s), PQFP32, LEAD FR

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