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IDT5T9955BFGI PDF预览

IDT5T9955BFGI

更新时间: 2024-11-20 14:51:23
品牌 Logo 应用领域
艾迪悌 - IDT 驱动逻辑集成电路
页数 文件大小 规格书
11页 133K
描述
PLL Based Clock Driver, 5T Series, 8 True Output(s), 0 Inverted Output(s), PBGA96, GREEN, FBGA-96

IDT5T9955BFGI 技术参数

是否无铅:不含铅是否Rohs认证:符合
生命周期:Obsolete零件包装代码:BGA
包装说明:LFBGA, BGA96,6X16,32针数:96
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.84Is Samacsys:N
系列:5T输入调节:STANDARD
JESD-30 代码:R-PBGA-B96JESD-609代码:e1
长度:13.5 mm逻辑集成电路类型:PLL BASED CLOCK DRIVER
最大I(ol):0.012 A湿度敏感等级:3
功能数量:2反相输出次数:
端子数量:96实输出次数:8
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:LFBGA
封装等效代码:BGA96,6X16,32封装形状:RECTANGULAR
封装形式:GRID ARRAY, LOW PROFILE, FINE PITCH峰值回流温度(摄氏度):260
电源:2.5 V认证状态:Not Qualified
Same Edge Skew-Max(tskwd):0.5 ns座面最大高度:1.5 mm
子类别:Clock Drivers最大供电电压 (Vsup):2.7 V
最小供电电压 (Vsup):2.3 V标称供电电压 (Vsup):2.5 V
表面贴装:YES温度等级:INDUSTRIAL
端子面层:Tin/Silver/Copper (Sn/Ag/Cu)端子形式:BALL
端子节距:0.8 mm端子位置:BOTTOM
处于峰值回流温度下的最长时间:30宽度:5.5 mm
最小 fmax:160 MHzBase Number Matches:1

IDT5T9955BFGI 数据手册

 浏览型号IDT5T9955BFGI的Datasheet PDF文件第2页浏览型号IDT5T9955BFGI的Datasheet PDF文件第3页浏览型号IDT5T9955BFGI的Datasheet PDF文件第4页浏览型号IDT5T9955BFGI的Datasheet PDF文件第5页浏览型号IDT5T9955BFGI的Datasheet PDF文件第6页浏览型号IDT5T9955BFGI的Datasheet PDF文件第7页 
2.5V PROGRAMMABLE  
SKEW DUAL PLL CLOCK  
DRIVER TURBOCLOCK™ W  
IDT5T9955  
FEATURES:  
DESCRIPTION:  
• Ref input is 3.3V tolerant  
The IDT5T9955 is a high fanout 2.5V PLL based clock driver intended  
forhighperformancecomputinganddata-communicationsapplications.A  
keyfeatureoftheprogrammableskewistheabilityofoutputstoleadorlag  
the REF input signal. The IDT5T9955 has sixteen programmable skew  
outputs in eight banks of 2. The two separate PLLs allow the user to  
independently control A and B banks. Skew is controlled by 3-level input  
signals that may be hard-wired to appropriate high-mid-low levels.  
The feedback input allows divide-by-functionality from 1 to 12 through  
the use of the xDS[1:0] inputs. This provides the user with frequency  
multiplication from 1 to 12 without using divided outputs for feedback.  
WhenthexsOEpinisheldlow, allthexbankoutputsaresynchronously  
enabled. However, ifxsOEisheldhigh, allthexbankoutputsexceptx2Q0  
and x2Q1 are synchronously disabled. The xLOCK output is high when  
the xbank PLL has achieved phase lock.  
• 8 pairs of programmable skew outputs  
• Low skew: 185ps same pair, 250ps same bank, 350ps both  
banks  
• Selectable positive or negative edge synchronization on each  
bank: excellent for DSP applications  
• Synchronous output enable on each bank  
• Input frequency: 2MHz to 160MHz  
• Output frequency: 6MHz to 160MHz  
• 3-level inputs for skew and PLL range control  
• 3-level inputs for feedback divide selection multiply / divide  
ratios of (1-6, 8, 10, 12) / (2, 4)  
• PLL bypass for DC testing  
• External feedback, internal loop filter  
• 12mA balanced drive outputs  
• Low Jitter: <100ps cycle-to-cycle  
• Power-down mode on each bank  
• Lock indicator on each bank  
Furthermore, when xPE is held high, all the outputs are synchronized  
withthepositiveedgeoftheREFclockinput. WhenxPEisheldlow, allthe  
outputsaresynchronizedwiththenegativeedgeofREF. TheIDT5T9955  
has LVTTL outputs with 12mA balanced drive outputs.  
• Available in BGA package  
FUNCTIONALBLOCKDIAGRAM  
ALOCK  
APE  
BPE  
AFS  
BFS  
BLOCK  
REF  
TEST  
BPD  
APD  
AsOE  
BsOE  
3
3
3
3
PLL  
PLL  
/ N  
/ N  
BFB  
AFB  
3
3
3
3
BDS1:0  
B1F1:0  
ADS1:0  
A1F1:0  
3
3
B1Q0  
B1Q1  
A1Q0  
A1Q1  
3
3
Skew  
Select  
Skew  
Select  
3
3
B2Q0  
B2Q1  
3
3
A2Q0  
A2Q1  
Skew  
Skew  
Select  
B2F1:0  
B3F1:0  
B4F1:0  
A2F1:0  
A3F1:0  
A4F1:0  
Select  
3
3
B3Q0  
B3Q1  
3
3
A3Q0  
A3Q1  
Skew  
Select  
Skew  
Select  
3
3
B4Q0  
B4Q1  
A4Q0  
A4Q1  
3
3
Skew  
Select  
Skew  
Select  
TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.  
INDUSTRIAL TEMPERATURE RANGE  
DECEMBER 2006  
1
c
2006 Integrated Device Technology, Inc.  
DSC 5976/13  

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