IDT5V2528/A
2.5/3.3VPHASE-LOCKLOOPCLOCKDRIVER
INDUSTRIALTEMPERATURERANGE
2.5V / 3.3V PHASE-LOCK
LOOP CLOCK DRIVER
ZERO DELAY BUFFER
IDT5V2528/A
The IDT5V2528 inputs, PLL core, Y0, Y1, andFBOUT buffers operate from
the 3.3V VDD and AVDD power supply pins.
FEATURES:
• Operates at 3.3V VDD/AVDD and 2.5V/3.3V VDDQ
• 1:10 fanout
One bank of ten outputs provide low-skew, low-jitter copies of CLK. Of
the ten outputs, up to seven may be configured for 2.5V or 3.3V LVTTL
outputs. The number of 2.5V outputs is controlled by 3-level input signals
G_CtrlandT_Ctrl, andbyconnectingtheappropriateVDDQ pinsto2.5Vor
3.3V. The 3-level input signals may be hard-wired to high-mid-low levels.
Outputsignaldutycyclesareadjustedto50percent,independentoftheduty
cycleatCLK. TheoutputscanbeenabledordisabledviatheG_Ctrl input.
When the G_Ctrl input is mid or high, the outputs switch in phase and
frequencywithCLK;whentheG_Ctrlislow, alloutputs(exceptFBOUT)are
disabledtothelogic-lowstate.
UnlikemanyproductscontainingPLLs,theIDT5V2528doesnotrequire
external RC networks. The loop filter for the PLL is included on-chip,
minimizing component count, board space, and cost.
Because it is based on PLL circuitry, the IDT5V2528 requires a
stabilization time to achieve phase lock of the feedback signal to the
referencesignal.Thisstabilizationtimeisrequired,followingpowerupand
• 3-level inputs for output control
• External feedback (FBIN) pin is used to synchronize the
outputs to the clock input signal
• No external RC network required for PLL loop stability
• Configurable 2.5V or 3.3V LVTTL outputs
• tPD Phase Error at 100MHz to 166MHz: ±150ps
• Jitter (peak-to-peak) at 133MHz and 166MHz: ±75ps
• Spread spectrum compatible
• Operating Frequency:
−
Std: 25MHz to 140MHz
A: 25MHz to 167MHz
−
• Available in TSSOP package
DESCRIPTION:
TheIDT5V2528isahighperformance, low-skew, low-jitter, phase-lock application of a fixed-frequency, fixed-phase signal at CLK, as well as
loop (PLL) clock driver. It uses a PLL to precisely align, in both frequency following any changes to the PLL reference or feedback signals. The PLL
and phase, the feedback (FBOUT) output to the clock (CLK) input signal. can be bypassed for test purposes by strapping AVDD to ground.
FUNCTIONALBLOCKDIAGRAM
28
G_Ctrl
3
1
T_Ctrl
TY0, VDDQ pin 4
TY1, VDDQ pin 25
26
24
TY2, VDDQ pin 25
TY3, VDDQ pin 15
TY4, VDDQ pin 15
MODE
SELECT
17
16
13
TY5, VDDQ pin 11
TY6, VDDQ pin 11
12
10
6
7
TY7, VDDQ pin 11
Y0, VDD pin 21
CLK
PLL
20
19
FBIN
AVDD
Y1, VDD pin 21
5
22
FBOUT, VDD pin 21
TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.
INDUSTRIAL TEMPERATURE RANGE
JUNE 2003
1
c
2002 Integrated Device Technology, Inc.
DSC 5971/11