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IDT5V50013DCG8 PDF预览

IDT5V50013DCG8

更新时间: 2024-11-24 20:59:23
品牌 Logo 应用领域
艾迪悌 - IDT 驱动光电二极管逻辑集成电路
页数 文件大小 规格书
8页 78K
描述
PLL Based Clock Driver, 5V Series, 1 True Output(s), 0 Inverted Output(s), CMOS, PDSO8, SOIC-8

IDT5V50013DCG8 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:SOIC
包装说明:SOIC-8针数:8
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.77
系列:5V输入调节:STANDARD
JESD-30 代码:R-PDSO-G8JESD-609代码:e3
长度:4.9 mm逻辑集成电路类型:PLL BASED CLOCK DRIVER
湿度敏感等级:1功能数量:1
反相输出次数:端子数量:8
实输出次数:1最高工作温度:70 °C
最低工作温度:封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE峰值回流温度(摄氏度):260
认证状态:Not Qualified座面最大高度:1.75 mm
最大供电电压 (Vsup):3.63 V最小供电电压 (Vsup):2.97 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:Matte Tin (Sn) - annealed端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:30宽度:3.9 mm
最小 fmax:140 MHzBase Number Matches:1

IDT5V50013DCG8 数据手册

 浏览型号IDT5V50013DCG8的Datasheet PDF文件第2页浏览型号IDT5V50013DCG8的Datasheet PDF文件第3页浏览型号IDT5V50013DCG8的Datasheet PDF文件第4页浏览型号IDT5V50013DCG8的Datasheet PDF文件第5页浏览型号IDT5V50013DCG8的Datasheet PDF文件第6页浏览型号IDT5V50013DCG8的Datasheet PDF文件第7页 
DATASHEET  
LOW EMI CLOCK GENERATOR  
IDT5V50013  
Description  
Features  
The IDT5V50013 generates a low EMI output clock from a  
clock input. The part is designed to dither the LCD interface  
clock for PDAs, printers, scanners, modems, copiers, and  
others. Using IDT’s proprietary mix of analog and digital  
Phase-Locked Loop (PLL) technology, the device spreads  
the frequency spectrum of the output, reducing the  
frequency amplitude peaks by several dB.  
Packaged in 8-pin SOIC  
Provides a spread spectrum output clock  
50 MHz to 140 MHz operation  
Accepts a clock input (provides same frequency dithered  
output)  
Center spread modulation  
IDT offers many other clocks for computers and computer  
peripherals. Consult IDT when you need to remove crystals  
and oscillators from your board.  
Peak reduction by 8 dB to 16 dB typical on 3rd through  
19th odd harmonics  
Low EMI feature can be disabled  
Operating voltage of 3.3 V  
Advanced, low-power CMOS process  
Block Diagram  
VDD  
2
S1:0  
SSCC  
PLL Clock  
Synthesis  
and Spread  
Spectrum  
Circuitry  
SSCLK  
ICLK  
GND  
IDT® LOW EMI CLOCK GENERATOR  
1
IDT5V50013 REV G 072412  

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