Datasheet > IDT5V19EE901

IDT5V19EE901

更新时间： 2024-09-28 11:16:03

品牌	Logo	应用领域
艾迪悌 - IDT		时钟发生器石英晶振压控振荡器可编程只读存储器电动程控只读存储器电可擦编程只读存储器
页数	文件大小	规格书
35页	734K
描述
EEPROM PROGRAMMABLE VCXO CLOCK GENERATOR

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中文翻译

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数据手册

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IDT5V19EE901 数据手册

DATASHEET

EEPROM PROGRAMMABLE VCXO CLOCK GENERATOR

IDT5V19EE901

Description

Features:

The IDT5V19EE901 is a programmable clock generator

intended for high performance data-communications,

telecommunications, consumer, and networking

applications. There are four internal PLLs, each individually

programmable, allowing for four unique non-integer-related

frequencies. The frequencies are generated from a single

reference clock. The reference clock can come from one of

the two redundant clock inputs. A glitchless automatic or

manual switchover function allows any one of the redundant

clocks to be selected during normal operation.

• Four internal PLLs

• Internal non-volatile EEPROM

• Fast (400kHz) mode I C serial interface

• Input frequency range: 1 MHz to 200 MHz

• Output frequency range: 4.9 kHz to 500 MHz

• Reference crystal input with programmable linear load

capacitance

– Crystal frequency range: 8 MHz to 50 MHz

(maximum crystal range is best effort)

The IDT5V19EE901 is in-system, programmable and can

be programmed through the use of I C interface. An

• Integrated VCXO

internal EEPROM allows the user to save and restore the

configuration of the device without having to reprogram it on

power-up.

• Each PLL has a 7-bit reference divider and a 12-bit

feedback-divider

• 8-bit output-divider blocks

Each of the four PLLs has an 7-bit reference divider and a

12-bit feedback divider. This allows the user to generate

four unique non-integer-related frequencies. The PLL loop

bandwidth is programmable to allow the user to tailor the

PLL response to the application. For instance, the user can

tune the PLL parameters to minimize jitter generation or to

maximize jitter attenuation. Spread spectrum generation

and/or fractional divides are allowed on two of the PLLs.

• Fractional division capability on one PLL

• Two of the PLLs support spread spectrum generation

capability

• I/O Standards:

– Outputs - 3.3 V LVTTL/ LVCMOS

– Outputs - LVPECL, LVDS and HCSL

– Inputs - 3.3 V LVTTL/ LVCMOS

• Programmable slew rate control

• Programmable loop bandwidth

• Programmable output inversion to reduce bimodal jitter

There are a total of six 8-bit output dividers. Each output

bank can be configured to support LVTTL, LVPECL, LVDS

or HCSL logic levels. Out0 (Output 0) supports 3.3V single

ended output only. The outputs are connected to the PLLs

via a switch matrix. The switch matrix allows the user to

route the PLL outputs to any output bank. This feature can

be used to simplify and optimize the board layout. In

addition, each output's slew rate and enable/disable

function is programmable.

• Redundant clock inputs with glitchless auto and manual

switchover options

• Individual output enable/disable

• Power-down mode

• 3.3V core V

• Available in TSSOP and VFQFPN packages

• -40 to +85 C Industrial Temp operation

IDT® EEPROM PROGRAMMABLE VCXO CLOCK GENERATOR

IDT5V19EE901 REV K 022310

12 3 4 5 6 7...35

中文翻译

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与IDT5V19EE901相关器件

型号	品牌	获取价格	描述	数据表
IDT5V19EE904	IDT	获取价格	EEPROM PROGRAMMABLE VCXO CLOCK GENERATOR
IDT5V2305	IDT	获取价格	2.5V TO 3.3V HIGH PERFORMANCE CLOCK BUFFER
IDT5V2305_10	IDT	获取价格	2.5V TO 3.3V HIGH PERFORMANCE CLOCK BUFFER
IDT5V2305NRGI	IDT	获取价格	暂无描述
IDT5V2305NRGI8	IDT	获取价格	Low Skew Clock Driver, 5V Series, 5 True Output(s), 0 Inverted Output(s), PQCC16, GREEN, T
IDT5V2305NRI	IDT	获取价格	2.5V TO 3.3V HIGH PERFORMANCE CLOCK BUFFER
IDT5V2305NRI8	IDT	获取价格	Low Skew Clock Driver, 5V Series, 5 True Output(s), 0 Inverted Output(s), PQCC16, THERMALL
IDT5V2305PGGI	IDT	获取价格	CLOCK BUFFER PERFORMANCE CLOCK BUFFER
IDT5V2305PGI	IDT	获取价格	2.5V TO 3.3V HIGH PERFORMANCE CLOCK BUFFER
IDT5V2305PGI8	IDT	获取价格	Low Skew Clock Driver, 5V Series, 5 True Output(s), 0 Inverted Output(s), PDSO16, TSSOP-16

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