IDT5T9891
INDUSTRIALTEMPERATURERANGE
EEPROMPROGRAMMABLE2.5VPROGRAMMABLESKEWPLLDIFFERENTIAL
EEPROM PROGRAMMABLE 2.5V
IDT5T9891
PROGRAMMABLE SKEW PLL
DIFFERENTIAL CLOCK DRIVER
FEATURES:
DESCRIPTION:
• 2.5VDD
The IDT5T9891is a 2.5VPLLdifferentialclockdriverintendedforhigh
performance computing and data-communications applications. A key
featureoftheprogrammableskewis theabilityofoutputs toleadorlagthe
REFinputsignal.TheIDT5T9891has sixdifferentialprogrammableskew
outputsinsixbanks,includingadedicateddifferentialfeedbackthroughthe
• 6 pairs of programmable skew outputs
• Low skew: 100ps all outputs at same interface level, 250ps all
outputs at different interface levels
• Selectable positive or negative edge synchronization
• Tolerant of spread spectrum input clock
• Synchronous output enable
2
use ofJTAGorI Cprogramming. The redundantinputcapabilityallows
fora smoothchange overtoa secondaryclocksource whenthe primary
clocksource is absent.
• Selectable inputs
• Input frequency: 4.17MHz to 250MHz
• Output frequency: 12.5MHz to 250MHz
• Internal non-volatile EEPROM
TheclockdrivercanbeconfiguredthroughtheuseofJTAG/I2Cprogram-
ming. An internal EEPROM will allow the user to save and restore the
configurationofthedevice.
2
• JTAG or I C bus serial interface for programming
The feedbackbankallows divide-by-functionalityfrom1to12through
2
• Hot insertable and over-voltage tolerant inputs
• Feedback divide selection with multiply ratios of (1-6, 8, 10, 12)
• Selectable HSTL, eHSTL, 1.8V/2.5V LVTTL, or LVEPECL input
interface
• Selectable HSTL, eHSTL, or 1.8V/2.5V LVTTL output interface for
each output bank
• Selectable differential or single-ended inputs and six differen-
tial outputs
• PLL bypass for DC testing
• External differential feedback, internal loop filter
• Low Jitter: <75ps cycle-to-cycle, all outputs at same interface
level: <100ps cycle-to-cycle all outputs at different interface
levels
theuseofJTAGorI Cprogramming. Thisprovidestheuserwithfrequency
multiplication1to12withoutusingdividedoutputsforfeedback. Eachoutput
bank also allows for a divide-by functionality of 2 or 4.
The IDT5T9891 features a user-selectable, single-ended or differential
input to six differential outputs. The differential clock driver also acts as a
translatorfromadifferentialHSTL,eHSTL,1.8V/2.5VLVTTL,LVEPECL,or
single-ended1.8V/2.5VLVTTLinputtoHSTL,eHSTL,or1.8V/2.5VLVTTL
outputs. EachoutputbankcanbeindividuallyconfiguredtobeeitherHSTL,
eHSTL,2.5VLVTTL,or1.8VLVTTL,includingthefeedbackbank. Also,each
clockinputcanbeindividuallyconfiguredtoaccept2.5VLVTTL,1.8VLVTTL,
ordifferentialsignals. Theoutputscanbesynchronouslyenabled/disabled.The
differentialoutputscanbesynchronouslyenabled/disabled.
Furthermore,alltheoutputscanbesynchronizedwiththepositiveedge
of the REF clock input or the negative edge of REF.
• Power-down mode
• Lock indicator
• Available in VFQFPN package
TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.
INDUSTRIAL TEMPERATURE RANGE
NOVEMBER 2004
1
c
2004 Integrated Device Technology, Inc.
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