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IDT5T9820NLGI PDF预览

IDT5T9820NLGI

更新时间: 2024-11-02 20:04:47
品牌 Logo 应用领域
艾迪悌 - IDT 驱动逻辑集成电路
页数 文件大小 规格书
36页 287K
描述
PLL Based Clock Driver, 5T Series, 10 True Output(s), 0 Inverted Output(s), GREEN, PLASTIC, VFQFPN-68

IDT5T9820NLGI 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:QFN包装说明:GREEN, PLASTIC, VFQFPN-68
针数:68Reach Compliance Code:compliant
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:5.79系列:5T
输入调节:MUXJESD-30 代码:S-XQCC-N68
JESD-609代码:e3长度:10 mm
逻辑集成电路类型:PLL BASED CLOCK DRIVER湿度敏感等级:3
功能数量:1反相输出次数:
端子数量:68实输出次数:10
最高工作温度:85 °C最低工作温度:-40 °C
输出特性:3-STATE封装主体材料:UNSPECIFIED
封装代码:HVQCCN封装形状:SQUARE
封装形式:CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE峰值回流温度(摄氏度):260
认证状态:Not QualifiedSame Edge Skew-Max(tskwd):0.25 ns
座面最大高度:1 mm最大供电电压 (Vsup):2.7 V
最小供电电压 (Vsup):2.3 V标称供电电压 (Vsup):2.5 V
表面贴装:YES温度等级:INDUSTRIAL
端子面层:MATTE TIN端子形式:NO LEAD
端子节距:0.5 mm端子位置:QUAD
处于峰值回流温度下的最长时间:30宽度:10 mm
最小 fmax:250 MHzBase Number Matches:1

IDT5T9820NLGI 数据手册

 浏览型号IDT5T9820NLGI的Datasheet PDF文件第2页浏览型号IDT5T9820NLGI的Datasheet PDF文件第3页浏览型号IDT5T9820NLGI的Datasheet PDF文件第4页浏览型号IDT5T9820NLGI的Datasheet PDF文件第5页浏览型号IDT5T9820NLGI的Datasheet PDF文件第6页浏览型号IDT5T9820NLGI的Datasheet PDF文件第7页 
IDT5T9820  
EEPROM PROGRAMMABLE  
2.5V ZERO DELAY PLL  
CLOCK DRIVER  
FEATURES:  
DESCRIPTION:  
• 2.5VDD  
The IDT5T9820 is a 2.5V PLL clock driver intended for high perfor-  
mancecomputinganddata-communicationsapplications. TheIDT5T9820  
hastenoutputsinfivebanksoftwo,plusadedicateddifferentialfeedback.  
The redundant input capability allows for a smooth change over to a  
secondary clock source when the primary clock source is absent.  
TheclockdrivercanbeconfiguredthroughtheuseofJTAG/I2Cprogram-  
ming. An internal EEPROM will allow the user to save and restore the  
configurationofthedevice.  
• 5 pairs of outputs  
Low skew: 100ps all outputs at same interface level, 250ps all  
outputs at different interface levels  
• Selectable positive or negative edge synchronization  
Tolerant of spread spectrum input clock  
• Synchronous output enable  
• Selectable inputs  
Input frequency: 4.17MHz to 250MHz  
• Output frequency: 12.5MHz to 250MHz  
Internal non-volatile EEPROM  
The feedbackbankallows divide-by-functionalityfrom1to12through  
theuseofJTAGorI Cprogramming. Thisprovidestheuserwithfrequency  
multiplication1to12withoutusingdividedoutputsforfeedback. Eachoutput  
bank also allows for a divide-by functionality of 2 or 4.  
2
2
• JTAG or I C bus serial interface for programming  
Hot insertable and over-voltage tolerant inputs  
• Feedback divide selection with multiply ratios of (1-6, 8, 10, 12)  
• Selectable HSTL, eHSTL, 1.8V/2.5V LVTTL, or LVEPECL input  
interface  
• Selectable HSTL, eHSTL, or 1.8V/2.5V LVTTL output interface for  
each output bank  
• Selectable differential or single-ended inputs and ten single-  
ended outputs  
• PLL bypass for DC testing  
• External differential feedback, internal loop filter  
Low Jitter: <75ps cycle-to-cycle, all outputs at same interface  
level: <100ps cycle-to-cycle all outputs at different interface  
levels  
The IDT5T9820 features a user-selectable, single-ended or differential  
inputtotensingle-endedoutputs. Theclockdriveralsoactsasatranslatorfrom  
a differential HSTL, eHSTL, 1.8V/2.5V LVTTL, LVEPECL, or single-ended  
1.8V/2.5VLVTTLinputtoHSTL,eHSTL,or1.8V/2.5VLVTTLoutputs. Each  
outputbankcanbe individuallyconfiguredtobe eitherHSTL, eHSTL, 2.5V  
LVTTL,or1.8VLVTTL,includingthefeedbackbank. Also,eachclockinput  
can be individually configured to accept 2.5V LVTTL, 1.8V LVTTL, or  
differentialsignals. Theoutputscanbesynchronouslyenabled/disabled.  
Furthermore,alltheoutputscanbesynchronizedwiththepositiveedge  
of the REF clock input or the negative edge of REF.  
• Power-down mode  
Lock indicator  
Available in VFQFPN package  
TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.  
INDUSTRIAL TEMPERATURE RANGE  
NOVEMBER 2004  
1
c
2004 Integrated Device Technology, Inc.  
DSC - 6503/24  

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