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IDT5T940 PDF预览

IDT5T940

更新时间: 2024-11-01 22:18:51
品牌 Logo 应用领域
艾迪悌 - IDT 时钟发生器
页数 文件大小 规格书
10页 68K
描述
PRECISION CLOCK GENERATOR OC-192 APPLICATIONS

IDT5T940 数据手册

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IDT5T940  
PRECISION CLOCK GENERATOR  
OC-192 APPLICATIONS  
FEATURES:  
DESCRIPTION:  
• Input frequency:  
The IDT5T940 generates a high precision FEC (Forward Error Cor-  
rection) or non-FEC source clock for SONET/SDH systems as well as a  
source clock for Gigabit Ethernet systems. This device also has clock  
regeneration capability: it creates a "clean" version of the clock input by  
using the internal oscillator to square the input clock's rising and falling  
edges and remove jitter. In the event that the main clock input fails, the  
device automatically locks to a backup reference clock using a hitless  
switchover mechanism.  
- ForSONETnon-FEC:19.44MHz,38.88MHz,77.76MHz,155.52MHz,  
311.04MHz, or 622.08MHz  
- For SONET FEC: 20.83MHz, 41.66MHz, 83.31MHz, 166.63MHz,  
333.26MHz, or 666.52MHz  
- For 10GE copper: 19.53MHz, 39.06MHz, 78.125MHz, 156.25MHz,  
312.5MHz, or 625MHz  
- For 10GE optical: 20.14MHz, 40.28MHz, 80.56MHz, 161.13MHz,  
322.26MHz, or 644.53MHz  
• 3-level inputs for feedback divide ratio and output frequency range  
selection  
• 1x, 2x, 4x, 8x, 16x, and 32x outputs on QOUT  
• Regenerated input clock or QOUT/4 on QREG  
• Lock indicator  
This device detects loss of valid CLKIN and leaves the VCO of the PLL at  
thelastvalidfrequencywhileanalternateinputREFINisselected. IfCLKIN  
andREFINaredifferentfrequencies,themultiplicationfactorwillbeadjustedto  
retainthesameoutputfrequency.  
TheIDT5T940canactasatranslatorfromadifferentialLVPECL,LVDS,or  
single-ended LVTTL input to LVPECL or LVDS outputs. The IDT5T940-10  
has LVDS outputs and the IDT5T940-30 has LVPECL outputs.  
ThethreemodesofoutputfrequencyrangearecontrolledbytheSELmode,  
whichisa3-levelpin. WhenSELmodeishighorlow,theQOUT isamultiplied  
versionoftheinputclockwhileQREGisaregeneratedversionoftheinputclock.  
WhenSELmodeismid,theQOUT isamultipliedversionoftheinputclockwhile  
QREG isQOUT/4.  
• Power-down mode  
• LVPECL or LVDS outputs  
• Three modes of output frequency range  
- Mode0:QOUT range155.5-166.6MHz. QREG isaregeneratedversion  
of the input clock.  
- Mode 1: QOUT range 622 - 666.5MHz. QREG output 155.5-166.6MHz.  
- Mode 2: QOUT range 622 - 666.5MHz. QREG is a regenerated version  
of the input clock frequency.  
TheIDT5T940featuresaselectableloopbandwidth.  
• Selectable loop bandwidths  
• Hitless switchover  
• Differential LVPECL, LVDS, or single-ended LVTTL input interface  
• 2.375 - 3.465V core and I/O  
APPLICATIONS:  
• Terabit routers  
• Gigabit ethernet systems  
• SONET / SDH systems  
• Digital cross connects  
• Optical transceiver modules  
• Available in VFQFPN package  
FUNCTIONALBLOCKDIAGRAM  
PLLBW1  
PLLBW0  
QREG  
QREG  
CLKIN  
CLKIN  
INPUT  
MUX  
DIVN  
DIVM  
PLL  
QOUT  
QOUT  
CONTROL  
LOGIC  
LOCK,  
FREQ.  
DETECTOR  
REFIN  
REFIN  
PD  
SELMODE  
LOCK  
CLK/  
REF0  
CLK/  
REF1  
TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.  
INDUSTRIAL TEMPERATURE RANGE  
DECEMBER 2003  
1
c
2003 Integrated Device Technology, Inc.  
DSC 6195/23  

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