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IDT5T940-10NLI8 PDF预览

IDT5T940-10NLI8

更新时间: 2024-11-20 20:05:19
品牌 Logo 应用领域
艾迪悌 - IDT 驱动逻辑集成电路
页数 文件大小 规格书
10页 64K
描述
PLL Based Clock Driver, 5T Series, 2 True Output(s), 0 Inverted Output(s), PQCC28, PLASTIC, VFQFPN-28

IDT5T940-10NLI8 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:QFN
包装说明:HVQCCN, LCC28,.24SQ,25针数:28
Reach Compliance Code:not_compliantHTS代码:8542.39.00.01
风险等级:5.91系列:5T
输入调节:DIFFERENTIAL MUXJESD-30 代码:S-PQCC-N28
JESD-609代码:e0长度:6 mm
逻辑集成电路类型:PLL BASED CLOCK DRIVER湿度敏感等级:1
功能数量:1反相输出次数:
端子数量:28实输出次数:2
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:HVQCCN
封装等效代码:LCC28,.24SQ,25封装形状:SQUARE
封装形式:CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE峰值回流温度(摄氏度):240
电源:2.5/3.3 V认证状态:Not Qualified
Same Edge Skew-Max(tskwd):0.02 ns座面最大高度:1 mm
子类别:Clock Driver最大供电电压 (Vsup):3.465 V
最小供电电压 (Vsup):2.375 V标称供电电压 (Vsup):2.5 V
表面贴装:YES温度等级:INDUSTRIAL
端子面层:Tin/Lead (Sn85Pb15)端子形式:NO LEAD
端子节距:0.65 mm端子位置:QUAD
处于峰值回流温度下的最长时间:20宽度:6 mm
最小 fmax:666.52 MHzBase Number Matches:1

IDT5T940-10NLI8 数据手册

 浏览型号IDT5T940-10NLI8的Datasheet PDF文件第2页浏览型号IDT5T940-10NLI8的Datasheet PDF文件第3页浏览型号IDT5T940-10NLI8的Datasheet PDF文件第4页浏览型号IDT5T940-10NLI8的Datasheet PDF文件第5页浏览型号IDT5T940-10NLI8的Datasheet PDF文件第6页浏览型号IDT5T940-10NLI8的Datasheet PDF文件第7页 
IDT5T940  
PRECISION CLOCK GENERATOR  
OC-192 APPLICATIONS  
FEATURES:  
DESCRIPTION:  
• Input frequency:  
The IDT5T940 generates a high precision FEC (Forward Error Cor-  
rection) or non-FEC source clock for SONET/SDH systems as well as a  
source clock for Gigabit Ethernet systems. This device also has clock  
regeneration capability: it creates a "clean" version of the clock input by  
using the internal oscillator to square the input clock's rising and falling  
edges and remove jitter. In the event that the main clock input fails, the  
device automatically locks to a backup reference clock using a hitless  
switchover mechanism.  
- ForSONETnon-FEC:19.44MHz,38.88MHz,77.76MHz,155.52MHz,  
311.04MHz, or 622.08MHz  
- For SONET FEC: 20.83MHz, 41.66MHz, 83.31MHz, 166.63MHz,  
333.26MHz, or 666.52MHz  
- For 10GE copper: 19.53MHz, 39.06MHz, 78.125MHz, 156.25MHz,  
312.5MHz, or 625MHz  
- For 10GE optical: 20.14MHz, 40.28MHz, 80.56MHz, 161.13MHz,  
322.26MHz, or 644.53MHz  
• 3-level inputs for feedback divide ratio and output frequency range  
selection  
• 1x, 2x, 4x, 8x, 16x, and 32x outputs on QOUT  
• Regenerated input clock or QOUT/4 on QREG  
• Lock indicator  
This device detects loss of valid CLKIN and leaves the VCO of the PLL at  
thelastvalidfrequencywhileanalternateinputREFINisselected. IfCLKIN  
andREFINaredifferentfrequencies,themultiplicationfactorwillbeadjustedto  
retainthesameoutputfrequency.  
TheIDT5T940canactasatranslatorfromadifferentialLVPECL,LVDS,or  
single-ended LVTTL input to LVPECL or LVDS outputs. The IDT5T940-10  
has LVDS outputs and the IDT5T940-30 has LVPECL outputs.  
ThethreemodesofoutputfrequencyrangearecontrolledbytheSELmode,  
whichisa3-levelpin. WhenSELmodeishighorlow,theQOUT isamultiplied  
versionoftheinputclockwhileQREGisaregeneratedversionoftheinputclock.  
WhenSELmodeismid,theQOUT isamultipliedversionoftheinputclockwhile  
QREG isQOUT/4.  
• Power-down mode  
• LVPECL or LVDS outputs  
• Three modes of output frequency range  
- Mode0:QOUT range155.5-166.6MHz. QREG isaregeneratedversion  
of the input clock.  
- Mode 1: QOUT range 622 - 666.5MHz. QREG output 155.5-166.6MHz.  
- Mode 2: QOUT range 622 - 666.5MHz. QREG is a regenerated version  
of the input clock frequency.  
TheIDT5T940featuresaselectableloopbandwidth.  
• Selectable loop bandwidths  
• Hitless switchover  
• Differential LVPECL, LVDS, or single-ended LVTTL input interface  
• 2.375 - 3.465V core and I/O  
APPLICATIONS:  
• Terabit routers  
• Gigabit ethernet systems  
• SONET / SDH systems  
• Digital cross connects  
• Optical transceiver modules  
• Available in VFQFPN package  
FUNCTIONALBLOCKDIAGRAM  
PLLBW1  
PLLBW0  
QREG  
QREG  
CLKIN  
CLKIN  
INPUT  
MUX  
DIVN  
DIVM  
PLL  
QOUT  
QOUT  
CONTROL  
LOGIC  
LOCK,  
FREQ.  
DETECTOR  
REFIN  
REFIN  
PD  
SELMODE  
LOCK  
CLK/  
REF0  
CLK/  
REF1  
TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.  
INDUSTRIAL TEMPERATURE RANGE  
DECEMBER 2003  
1
c
2003 Integrated Device Technology, Inc.  
DSC 6195/23  

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