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IDT5T93GL06NLI PDF预览

IDT5T93GL06NLI

更新时间: 2024-11-02 02:59:23
品牌 Logo 应用领域
艾迪悌 - IDT 时钟
页数 文件大小 规格书
15页 108K
描述
2.5V LVDS 1:6 GLITCHLESS CLOCK BUFFER TERABUFFER-TM II

IDT5T93GL06NLI 技术参数

是否无铅: 不含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:QFN
包装说明:HVQCCN, LCC28,.24SQ,25针数:28
Reach Compliance Code:not_compliantHTS代码:8542.39.00.01
风险等级:5.92系列:5T
输入调节:DIFFERENTIAL MUXJESD-30 代码:S-PQCC-N28
JESD-609代码:e0长度:6 mm
逻辑集成电路类型:LOW SKEW CLOCK DRIVER湿度敏感等级:1
功能数量:1反相输出次数:
端子数量:28实输出次数:6
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:HVQCCN
封装等效代码:LCC28,.24SQ,25封装形状:SQUARE
封装形式:CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE峰值回流温度(摄氏度):240
电源:2.5 VProp。Delay @ Nom-Sup:2 ns
传播延迟(tpd):2 ns认证状态:Not Qualified
Same Edge Skew-Max(tskwd):0.025 ns座面最大高度:1 mm
子类别:Clock Drivers最大供电电压 (Vsup):2.7 V
最小供电电压 (Vsup):2.3 V标称供电电压 (Vsup):2.5 V
表面贴装:YES温度等级:INDUSTRIAL
端子面层:Tin/Lead (Sn85Pb15)端子形式:NO LEAD
端子节距:0.65 mm端子位置:QUAD
处于峰值回流温度下的最长时间:20宽度:6 mm
最小 fmax:800 MHzBase Number Matches:1

IDT5T93GL06NLI 数据手册

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2.5V LVDS 1:6 GLITCHLESS  
IDT5T93GL06  
CLOCK BUFFER  
TERABUFFER™ II  
DESCRIPTION:  
FEATURES:  
TheIDT5T93GL062.5Vdifferentialclockbufferisauser-selectablediffer-  
• Guaranteed Low Skew < 25ps (max)  
• Very low duty cycle distortion < 100ps (max)  
• High speed propagation delay < 2ns (max)  
• Up to 800MHz operation  
entialinputtosixLVDSoutputs. ThefanoutfromadifferentialinputtosixLVDS  
outputsreducesloadingontheprecedingdriverandprovidesanefficientclock  
distributionnetwork. TheIDT5T93GL06canactasatranslatorfromadifferential  
HSTL, eHSTL, LVEPECL (2.5V), LVPECL (3.3V), CML, or LVDS input to  
LVDS outputs. A single-ended 3.3V / 2.5V LVTTL input can also be used to  
translatetoLVDSoutputs. Theredundantinputcapabilityallowsforaglitchless  
change-over from a primary clock source to a secondary clock source up to  
650MHz. SelectableinputsarecontrolledbySEL. Duringtheswitchover,the  
outputwilldisablelowforuptothreeclockcyclesofthepreviously-selectedinput  
clock. The outputs will remain low for up to three clock cycles of the newly-  
selectedclock,afterwhichtheoutputswillstartfromthenewly-selectedinput.  
AFSELpinhasbeenimplementedtocontroltheswitchoverincaseswherea  
clocksourceisabsentorisdriventoDClevelsbelowtheminimumspecifications.  
The IDT5T93GL06 outputs can be asynchronously enabled/disabled.  
Whendisabled,theoutputswilldrivetothevalueselectedbytheGLpin. Multiple  
power and grounds reduce noise.  
• Glitchless input clock switching up to 650MHz  
• Selectable inputs  
• Hot insertable and over-voltage tolerant inputs  
• 3.3V / 2.5V LVTTL, HSTL, eHSTL, LVEPECL (2.5V), LVPECL (3.3V),  
CML, or LVDS input interface  
• Selectable differential inputs to six LVDS outputs  
• Power-down mode  
• 2.5V VDD  
• Available in VFQFPN package  
APPLICATIONS:  
• Clock distribution  
FUNCTIONALBLOCKDIAGRAM  
GL  
G
Q1  
OUTPUT  
CONTROL  
Q1  
PD  
Q2  
Q2  
OUTPUT  
CONTROL  
A1  
1
A1  
Q3  
Q3  
OUTPUT  
CONTROL  
A2  
Q4  
Q4  
OUTPUT  
CONTROL  
0
A2  
Q5  
Q5  
OUTPUT  
CONTROL  
SEL  
FSEL  
Q6  
Q6  
OUTPUT  
CONTROL  
TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.  
INDUSTRIAL TEMPERATURE RANGE  
OCTOBER 2003  
1
© 2003 Integrated Device Technology, Inc.  
DSC-6183/8  

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