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ICS93705FLF-T PDF预览

ICS93705FLF-T

更新时间: 2024-09-16 14:51:23
品牌 Logo 应用领域
艾迪悌 - IDT 光电二极管
页数 文件大小 规格书
8页 100K
描述
Clock Driver, PDSO48

ICS93705FLF-T 技术参数

是否Rohs认证: 符合生命周期:Obsolete
Reach Compliance Code:unknown风险等级:5.84
JESD-30 代码:R-PDSO-G48JESD-609代码:e3
最大I(ol):0.001 A湿度敏感等级:1
端子数量:48最高工作温度:70 °C
最低工作温度:封装主体材料:PLASTIC/EPOXY
封装代码:SSOP封装等效代码:SSOP48,.4
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, SHRINK PITCH
电源:2.5 VProp。Delay @ Nom-Sup:6 ns
认证状态:Not Qualified子类别:Clock Drivers
标称供电电压 (Vsup):2.5 V表面贴装:YES
温度等级:COMMERCIAL端子面层:Matte Tin (Sn) - annealed
端子形式:GULL WING端子节距:0.635 mm
端子位置:DUALBase Number Matches:1

ICS93705FLF-T 数据手册

 浏览型号ICS93705FLF-T的Datasheet PDF文件第2页浏览型号ICS93705FLF-T的Datasheet PDF文件第3页浏览型号ICS93705FLF-T的Datasheet PDF文件第4页浏览型号ICS93705FLF-T的Datasheet PDF文件第5页浏览型号ICS93705FLF-T的Datasheet PDF文件第6页浏览型号ICS93705FLF-T的Datasheet PDF文件第7页 
ICS93705  
Integrated  
Circuit  
Systems,Inc.  
DDR Phase Lock Loop Zero Delay Clock Buffer  
RecommendedApplication:  
DDR Zero Delay Clock Buffer  
Pin Configuration  
GND  
CLKC0  
CLKT0  
VDD  
CLKT1  
CLKC1  
GND  
1
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
GND  
CLKC5  
CLKT5  
VDD  
CLKT6  
CLKC6  
GND  
ProductDescription/Features:  
Low skew, low jitter PLL clock driver  
I2C for functional and output control  
Feedback pins for input to output synchronization  
Spread Spectrum tolerant inputs  
GND  
GND  
CLKC2  
CLKT2  
VDD  
SCLK  
CLK_INT  
N/C  
CLKC7  
CLKT7  
VDD  
SDATA  
N/C  
FB_INT  
VDD  
FB_OUTT  
N/C  
GND  
CLKC8  
CLKT8  
VDD  
CLKT9  
CLKC9  
GND  
3.3V tolerant CLK_INT input  
SwitchingCharacteristics:  
VDD  
PEAK - PEAK jitter (66MHz): <120ps  
PEAK - PEAK jitter (>100MHz): <75ps  
CYCLE - CYCLE jitter (66MHz):<120ps  
CYCLE - CYCLE jitter (>100MHz):<65ps  
OUTPUT - OUTPUT skew: <100ps  
Output Rise and Fall Time: 450ps - 950ps  
DUTY CYCLE: 49% - 51%  
AVDD  
AGND  
GND  
CLKC3  
CLKT3  
VDD  
CLKT4  
CLKC4  
GND  
48-Pin SSOP  
Block Diagram  
Functionality  
INPUTS  
OUTPUTS  
PLL State  
AVDD CLK_INT CLKT CLKC FB_OUTT  
FB_OUTT  
2.5V  
(nom)  
CLKT0  
CLKC0  
L
H
L
H
Z
H
L
L
H
Z
on  
on  
off  
CLKT1  
CLKC1  
2.5V  
(nom)  
Control  
SCLK  
CLKT2  
CLKC2  
2.5V  
(nom)  
<20MHz(1)  
Z
Logic  
SDATA  
CLKT3  
CLKC3  
GND  
GND  
L
L
H
L
L
Bypassed/off  
Bypassed/off  
CLKT4  
CLKC4  
H
H
H
CLKT5  
CLKC5  
FB_INT  
PLL  
CLKT6  
CLKC6  
CLK_INT  
CLKT7  
CLKC7  
CLKT8  
CLKC8  
CLKT9  
CLKC9  
0418D—04/28/05  

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