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ICS9341YFLF

更新时间: 2024-09-16 19:54:03
品牌 Logo 应用领域
艾迪悌 - IDT 时钟光电二极管外围集成电路晶体
页数 文件大小 规格书
9页 207K
描述
Processor Specific Clock Generator, 133.3MHz, PDSO48, SSOP-48

ICS9341YFLF 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:SSOP
包装说明:SSOP,针数:48
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.25
JESD-30 代码:R-PDSO-G48JESD-609代码:e3
长度:15.875 mm端子数量:48
最高工作温度:70 °C最低工作温度:
最大输出时钟频率:133.3 MHz封装主体材料:PLASTIC/EPOXY
封装代码:SSOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, SHRINK PITCH峰值回流温度(摄氏度):260
主时钟/晶体标称频率:16 MHz认证状态:Not Qualified
座面最大高度:2.794 mm最大供电电压:3.465 V
最小供电电压:3.135 V标称供电电压:3.3 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:MATTE TIN
端子形式:GULL WING端子节距:0.635 mm
端子位置:DUAL处于峰值回流温度下的最长时间:30
宽度:7.5 mmuPs/uCs/外围集成电路类型:CLOCK GENERATOR, PROCESSOR SPECIFIC
Base Number Matches:1

ICS9341YFLF 数据手册

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Integrated  
Circuit  
Systems, Inc.  
ICS9341  
133MHz Clock Generator and Integrated Buffer for PowerPC™  
General Description  
Features  
The ICS9341 generates all clocks required for high speed Generates the following system clocks:  
PowerPC RISC microprocessor systems. Generating clocks in  
phase with an external reference frequency.  
- 4-CPUA(3.3V, upto133MHz)  
- 4-CPUB(3.3V, upto133MHz)  
- 8-PCI(3.3V,33.3MHz)  
Spread Spectrum may be enabled by driving the SS_EN pin  
active. Spread spectrum typically reduces system EMI by 8dB  
to 10dB. This simplifies EMI qualification without resorting to  
board design iterations or costly shielding. The ICS9341  
employs a proprietary closed loop design, which tightly  
controls the percentage of spreading over process and  
temperature variations.  
- 1-OUT(3.3v, 64MHz)  
- 1-OUT/2(3.3V,OUT/2MHz)  
- 2-REF(3.3V,14.318MHz)  
•
•
•
Up to 133MHz frequency support.  
Stop clocks for power management  
Spread Spectrum for EMI control  
±.25% center spread  
Skew characteristics:  
- CPU-CPU:<350ps  
- CPU-PCI:<500ps  
- PCI-PCI:<500ps  
Block Diagram  
X1  
REF (0:1)  
OSC  
2
4
X2  
/ 4  
/ 2  
CPUCLKA (1:4)  
Pin Configuration  
PLL  
Spread  
Spectrum  
GNDREF  
X1  
1
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
REF1  
REF0  
CPUCLKB (1:4)  
STOP  
4
X2  
VDDREF  
CPUA1  
CPUA2  
SS_EN  
GNDCPUA  
OUT_SEL1*  
PD#  
VDDCPUA  
CPUA3  
CPUA4  
CPUB_STOP#**  
VDDD  
VDDOUT  
OUT  
OUT/2  
GNDOUT  
GNDA  
GNDD  
VDDPCI  
PCICLK1  
PCICLK2  
PCICLK3  
PCICLK4  
GNDPCI  
GNDCPUB  
CPUB1  
C
o
n
t
CPUB_STOP#  
OUT_SEL (0:1)  
PCI_STOP#  
SS_EN  
/ 3  
/ 6  
/ 5  
PLL2  
r
o
l
OUT  
/ 2  
OUT/2  
CPUB2  
CPUB3  
CPUB4  
PD#  
VDDCPUB  
VDDPCI  
PCICLK5  
PCICLK6  
PCICLK7  
PCICLK8  
FS0  
FS1  
*OUT_SEL0  
GNDPCI  
/ 4  
/ 5  
/ 6  
/ 8  
PCICLK (1:8)  
STOP  
8
N/C  
N/C  
*PCI_STOP#  
VDDA  
Power Groups:  
VDDREF,GNDREF=REF,X1,X2  
GNDPCI,VDDPCI=PCICLK  
VDD66,GND66=3V66  
VDD48,GND48=48MHz  
VDDCOR,GNDCOR=PLLCore  
48-pin SSOP  
* Internal pull-up resistor of 120K to 3.3V on  
indicated inputs  
** Internal pull-down resistor of 120K to GND  
on indicated inputs.  
VDDLCPU/2,GNDLCPU/2=CPU/2  
VDDLIOAPIC,GNDIOAPIC=IOAPIC  
ICS reserves the right to make changes in the device data identified in  
this publication without further notice. ICS advises its customers to  
obtain the latest version of all device data to verify that any  
9341 Rev A 10/12/99  
information being relied upon by the customer is current and accurate.  

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