Datasheet > ICS93701

ICS93701

更新时间： 2024-09-16 04:44:23

品牌	Logo	应用领域
矽成 - ICSI		时钟驱动器双倍数据速率
页数	文件大小	规格书
9页	175K
描述
DDR Phase Lock Loop Clock Driver

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中文翻译

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数据手册

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ICS93701 数据手册

ICS93701

Integrated

Circuit

Systems, Inc.

DDR Phase Lock Loop Clock Driver

RecommendedApplication:

DDR Clock Driver

Pin Configuration

GND

CLKC0

CLKT0

VDD

CLKT1

CLKC1

GND

ProductDescription/Features:

CLKC5

CLKT5

VDD

CLKT6

CLKC6

GND

•

Low skew, low jitter PLL clock driver

I²C for functional and output control

Feedback pins for input to output synchronization

Spread Spectrum tolerant inputs

GND

CLKC2

CLKT2

VDD

CLKC7

CLKT7

VDD

SDATA

FB_INC

FB_INT

VDD

FB_OUTT

FB_OUTC

GND

CLKC8

CLKT8

VDD

SwitchingCharacteristics:

SCLK

•

PEAK - PEAK jitter (66MHz): <120ps

PEAK - PEAK jitter (>100MHz): <75ps

CYCLE - CYCLE jitter (66MHz):<120ps

CYCLE - CYCLE jitter (>100MHz):<65ps

OUTPUT - OUTPUT skew: <100ps

DUTY CYCLE: 49.5% - 50.5%

CLK_INT

CLK_INC

VDDI²C

AVDD

AGND

GND

CLKC3

CLKT3

VDD

CLKT4

CLKC4

GND

CLKT9

CLKC9

GND

Slew rate: 1V/ns - 2V/ns

48-Pin TSSOP

Block Diagram

Functionality

INPUTS

OUTPUTS

PLL State

AVDD CLK_INT CLK_INC CLKT CLKC FB_OUTT FB_OUTC

2.5V

(nom)

FB_OUTT

FB_OUTC

off

2.5V

(nom)

CLKT0

CLKC0

2.5V

(nom)

<20MHz)⁽¹⁾

CLKT1

CLKC1

Control

SCLK

CLKT2

CLKC2

Logic

SDATA

CLKT3

CLKC3

CLKT4

CLKC4

FB_INT

FB_INC

CLKT5

CLKC5

PLL

CLK_INC

CLK_INT

CLKT6

CLKC6

CLKT7

CLKC7

CLKT8

CLKC8

CLKT9

CLKC9

0417B—10/29/02

12 3 4 5 6 7...9

中文翻译

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与ICS93701相关器件

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