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ICS9248-134 PDF预览

ICS9248-134

更新时间: 2024-11-10 22:11:03
品牌 Logo 应用领域
矽成 - ICSI /
页数 文件大小 规格书
13页 295K
描述
Frequency Timing Generator for PENTIUM II/III Systems

ICS9248-134 数据手册

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Integrated  
Circuit  
Systems, Inc.  
ICS9248-134  
Frequency Timing Generator for PENTIUM II/III Systems  
Recommended Application:  
For Intel Camino Style Chipsets  
Pin Configuration  
GND  
REF0  
*SEL24_48#/REF1  
VDDREF  
X1  
1
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
VDDL  
IOAPIC0  
IOAPIC1  
GND  
IOAPIC2  
VDDL  
OutputFeatures:  
3 - CPUs @ 2.5V, up to 180MHz.  
1 - CPU/2 @ 2.5V.  
X2  
GND  
CPU/2  
GND  
*FS0/PCICLK_F  
*FS1/PCICLK0  
VDDPCI  
*FS2/PCICLK1  
*FS3/PCICLK2  
GND  
CPUCLK0  
VDDL  
CPUCLK1  
CPUCLK2  
GND  
VDD66  
3V66_0  
3V66_1  
3V66_2  
GND66  
SDATA  
3 - IOAPIC @ 2.5V, PCI or PCI/2  
3 - 3V66MHz @ 3.3V.  
11 - PCIs @ 3.3V  
PCICLK3  
PCICLK4  
VDDPCI  
PCICLK5  
PCICLK6  
GND  
PCICLK7  
PCICLK8  
PCICLK9  
VDDPCI  
1 - 48MHz, @ 3.3V fixed  
1 - 24/48MHz, @ 3.3V  
SCLK  
Features:  
VDD48  
48MHz/FS4*  
24_48MHz  
GND48  
Support power management: Power down Mode  
from I2C programming.  
PD#  
Spread spectrum for EMI control  
± 0.25% center spread).  
48-pin SSOP  
*120K ohm pull-up to VDD on indicated inputs.  
Uses external 14.318MHz crystal  
Key Specifications:  
Functionality  
FS4 FS3 FS2 FS1 FS0  
CPU Output Jitter: <250ps  
CPU  
103.00 34.33  
105.00 35.00  
PCI  
3V66  
68.67  
70.00  
IOAPIC  
17.17  
17.50  
IOAPIC Output Jitter: <500ps  
48MHz, 3V66, PCI Output Jitter: <500ps)  
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
100.45 33.483 66.967 16.742  
100.90 33.63 67.27 16.82  
107.10 35.700 71.400 17.850  
109.00 36.33  
112.00 37.34  
114.00 28.50  
116.00 29.00  
118.00 29.50  
133.30 33.33  
120.00 30.00  
122.00 30.50  
125.00 31.25  
72.67  
74.67  
57.00  
58.00  
59.00  
66.65  
60.00  
61.00  
62.50  
18.17  
18.67  
14.25  
14.50  
14.75  
16.66  
15.00  
15.25  
15.63  
Block Diagram  
PLL2  
48MHz  
24_48MHz  
/ 2  
X1  
X2  
XTAL  
OSC  
REF (1:0)  
128.21 32.05 64.105 16.026  
130.00 32.50  
132.00 33.00  
133.90 33.48  
138.00 34.50  
142.00 35.50  
146.00 36.50  
150.00 37.50  
153.00 38.25  
156.00 39.00  
159.00 39.75  
162.00 40.50  
165.00 41.25  
168.00 42.00  
171.00 42.75  
174.00 43.50  
177.00 44.25  
180.00 45.00  
65.00  
66.00  
66.95  
69.00  
71.00  
73.00  
75.00  
76.50  
78.00  
79.50  
81.00  
82.50  
84.00  
85.50  
87.00  
88.50  
90.00  
16.25  
16.50  
16.74  
17.25  
17.75  
18.25  
18.75  
19.13  
19.50  
19.88  
20.25  
20.63  
21.00  
21.38  
21.75  
22.13  
22.50  
PLL1  
Spread  
Spectrum  
CPU  
DIVDER  
CPUCLK (2:0)  
CPU/2  
/ 2  
SEL24_48#  
FREQ_APIC  
IOAPIC  
DIVDER  
IOAPIC (2:0)  
Control  
Logic  
SDATA  
SCLK  
PCI  
DIVDER  
PCICLK (9:0)  
PCICLK_F  
FS (4:0)  
PD#  
Config.  
Reg.  
3V66  
DIVDER  
3V66 (2:0)  
ICS reserves the right to make changes in the device data identified in  
this publication without further notice. ICS advises its customers to  
obtain the latest version of all device data to verify that any  
9248-134Rev A8/22/00  
information being relied upon by the customer is current and accurate.  

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