Datasheet > ICS9248-65

ICS9248-65

更新时间： 2024-09-24 22:55:27

品牌	Logo	应用领域
矽成 - ICSI		/
页数	文件大小	规格书
10页	266K
描述
Frequency Timing Generator for PENDIUM II Systems

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ICS9248-65 数据手册

Integrated

Circuit

Systems, Inc.

ICS9248-65

Frequency Timing Generator for PENTIUM II Systems

Features

Key Specification

CPU Output Jitter: <250ps

Generates the following system clocks:

-3 CPUclocks(2.5V,100/133MHz)

CPU/2 Output Jitter. <250ps

IOAPIC Output Jitter: <500ps

48MHz, 3V66, PCIOutputJitter:<500ps

PCI Output Jitter. <500ps

Ref Output Jitter. <1000ps

CPU 0:2 Output Skew: <175ps

PCI_F, PCI1:7OutputSkew:<500ps

3V66_0:2OutputSkew<250ps

CPU to 3V66_0:2 Output Offset: 0.0 - 1.5ns (CPU leads)

3V66 to PCI Output Offset: 1.5 - 4ns (CPU leads)

CPU to IOAPIC Output Offset 1.5 - 4.0ns (CPU leads)

- 10 PCI clocks, including 1 free-running

(3.3V, 33.3MHz)

-1CPU/2clocks(2.5V, 50/66.6MHz)

-1IOAPICclocks(2.5V,16.67MHz)

-3Fixedfrequency66MHzclocks(3.3V, 66.6MHz)

-2REFclocks(3.3V,14.318MHz)

-1USBclock(3.3V,48MHz)

Efficient power management through PD#.

0 to -0.5% typical down spread modulation on CPU, PCI,

IOAPIC, 3V66 and CPU/2 output clocks.

Usesexternal14.318MHzcrystal.

Block Diagram

Pin Configuration

48-pin SSOP

Third party brands and names are the property of their respective owners.

9248-65 Rev C 7/28/99

ICS reserves the right to make changes in the device data identified in

this publication without further notice. ICS advises its customers to

obtain the latest version of all device data to verify that any

information being relied upon by the customer is current and accurate.

12 3 4 5 6 7...10

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