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ICS9248-72 PDF预览

ICS9248-72

更新时间: 2024-11-10 22:55:27
品牌 Logo 应用领域
矽成 - ICSI /
页数 文件大小 规格书
12页 554K
描述
Frequency Timing Generator for PENTIUM II Systems

ICS9248-72 数据手册

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ICS9248-72  
Integrated  
Circuit  
Systems, Inc.  
Preliminary Product Preview  
Frequency Timing Generator for PENTIUM II Systems  
General Description  
Features  
The ICS9248-72 is a main clock synthesizer chip for Pentium  
II based systems using Rambus Interface DRAMs. This chip  
provides all the clocks required for such a system when used  
with a Direct Rambus Clock Generator(DRCG) chip such as  
theICS9211-01.  
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Up to 200MHz frequency support.  
Power Down feature.  
Spread Spectrum for EMI control  
(0 to –0.5% down spread , + 0.25% center spread)  
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I2Cinterface.  
Spread Spectrum may be enabled by driving the SPREAD#  
pin active. Spread spectrum typically reduces system EMI by  
8dBto10dB. ThissimplifiesEMIqualificationwithoutresorting  
to board design iterations or costly shielding. The ICS9248-  
72 employs a proprietary closed loop design, which tightly  
controls the percentage of spreading over process and  
temperature variations.  
VDDL=2.5V,VDD=3.3V  
Key Specification  
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•
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•
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CPU Output Jitter: <250ps  
CPU/2 Output Jitter. <250ps  
IOAPIC Output Jitter: <500ps  
48MHz, 3V66, PCIOutputJitter:<500ps  
Ref Output Jitter. <1000ps  
CPUOutputSkew:<175ps  
IOAPIC Output Skew <250ps  
PCI Output Skew: <500ps  
3V66OutputSkew<250ps  
The CPU/2 clocks are inputs to the DRCG.  
CPU to 3V66 Output Offset: 0.0 - 1.5ns (CPU leads)  
3V66 to PCI Output Offset: 1.5 - 4.0ns (3V66 leads)  
CPU to IOAPIC Output Offset 1.5 - 4.0ns (CPU leads)  
Block Diagram  
Pin Configuration  
48-pin SSOP  
* 250K ohm pull-up to VDD on indicated inputs.  
1.These pins will have 2X drive strength  
PRODUCT PREVIEW documents contain information on new  
products in the sampling or preproduction phase of development.  
Characteristic data and other specifications are subject to change  
without notice.  
9248-72RevB7/28/99  

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