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ICS9248-135 PDF预览

ICS9248-135

更新时间： 2024-09-28 22:11:03
品牌 Logo 应用领域
矽成 - ICSI /
页数 文件大小 规格书
15页 192K
描述
Frequency Generator & Integrated Buffers for Celeron & PII/III⑩& K6

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ICS9248-135 数据手册

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Integrated  
Circuit  
Systems, Inc.  
ICS9248-135  
Frequency Generator & Integrated Buffers for Celeron & PII/III™& K6  
Recommended Application:  
Motherboard Single chip clock solution for SIS540,  
SIS630 Pentium II/III and K6 chipsets.  
Pin Configuration  
VDDREF  
*1REF0/FS3  
GNDREF  
X1  
1
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
REF1  
VDDLCPU  
CPUCLK_F  
CPUCLK1  
GNDL  
CPUCLK2  
VDD  
SDRAM_F1  
SDRAM_F0  
GND  
SDRAM7  
SDRAM6  
VDD  
SDRAM5  
SDRAM4  
GND  
SDRAM3  
SDRAM2  
VDD  
Output Features:  
X2  
•
•
3- CPUs @ 2.5/3.3V, up to 166MHz.  
VDDPCI  
*PCICLK_F/FS1  
*PCICLK1/FS2  
PCICLK2  
GNDPCI  
PCICLK3  
PCICLK4  
PCICLK5  
PCICLK6  
VDD  
10 - SDRAM @ 3.3V, up to 166MHz  
including 2 SDRAM_F's  
•
•
•
7- PCI @3.3V,  
1- 48MHz, @3.3V fixed.  
1- 24/48MHz, @3.3V selectable by I2C  
(Default is 24MHz).  
GND  
SDRAM_STOP#  
**PD#  
•
2- REF @3.3V, 14.318MHz.  
VDD  
Features:  
CPU_STOP#  
PCI_STOP#  
GND  
SDRAM1  
SDRAM0  
VDD  
•
•
•
Up to 166MHz frequency support  
Support FS0-FS3 trapping status bit for I2C read back.  
SDATA  
SCLK  
48MHz/FS0*1  
24_48MHz/CPU2.5_3.3#*  
Support power management: CPU, PCI, SDRAM stop  
and Power down Mode form I2C programming.  
48-Pin 300mil SSOP  
* These inputs have a 120K pull down to GND.  
** These inputs have a 120K pullup to VDD.  
1 These are double strength.  
•
•
Spread spectrum for EMI control (0 to -0.5%, 0.25%).  
FS0, FS1, FS3 must have a internal 120K pull-Down  
to GND.  
•
Uses external 14.318MHz crystal  
Skew Specifications:  
•
•
•
•
•
CPU - CPU: < 175ps  
SDRAM - SDRAM < 250ps  
PCI - PCI: < 500ps  
CPU - SDRAM: < 500ps  
CPU (early) - PCI: 1-4ns (typ. 2ns)  
Functionality  
Block Diagram  
CPU  
(MHz)  
66.6  
100.0  
150.0  
133.3  
66.8  
100.0  
100.0  
133.3  
66.8  
97.0  
70.0  
95.0  
95.0  
112.0  
97.0  
96.2  
SDRAM PCICLK  
FS3 FS2 FS1 FS0  
(MHz)  
100.0  
100.0  
100.0  
100.0  
133.6  
133.3  
150.0  
133.3  
66.8  
(MHz)  
33.3  
33.3  
37.5  
33.3  
33.4  
33.3  
37.5  
33.3  
33.4  
32.3  
35.0  
31.7  
31.7  
37.3  
32.2  
32.1  
PLL2  
48MHz  
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
24_48MHz  
/ 2  
X1  
X2  
XTAL  
OSC  
REF[1:0]  
2
2
PLL1  
Spread  
Spectrum  
CPU  
DIVDER  
Stop  
CPUCLK [2:1]  
CPUCLK_F  
SDRAM  
DIVDER  
Stop  
Stop  
SDRAM [7:0]  
8
CPU2.5_3.3#  
97.0  
105.0  
95.0  
SDRAM_F [1:0]  
2
6
Control  
Logic  
SDATA  
SCLK  
PCI  
DIVDER  
PCICLK [6:1]  
PCICLK_F  
FS[3:0]  
126.7  
112.0  
129.3  
96.2  
PD#  
PCI_STOP#  
Config.  
Reg.  
CPU_STOP#  
SDRAM_STOP#  
ICS reserves the right to make changes in the device data identified in  
this publication without further notice. ICS advises its customers to  
obtain the latest version of all device data to verify that any  
9248-135 Rev A 1/16/01  
Third party brands and names are the property of their respective owners.  
information being relied upon by the customer is current and accurate.  
1234567...15

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