Datasheet > ICS9248-55

ICS9248-55

更新时间： 2024-11-10 22:55:27

品牌	Logo	应用领域
矽成 - ICSI		时钟
页数	文件大小	规格书
10页	271K
描述
Pentium/Pro/IITM System Clock Chip

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ICS9248-55 数据手册

Integrated

Circuit

Systems, Inc.

ICS9248-55

Pentium/Pro/II System Clock Chip

General Description

Features

Generates system clocks for CPU, IOAPIC, PCI, plus

The ICS9248-55 is a Clock Synthesizer chip for Pentium and

PentiumPro CPU based Desktop/Notebook systems that will

provide all necessary clock timing.

14.314MHzREF(0:2), USB, andSuperI/O

Supports single or dual processor systems

Supports Spread Spectrum modulation for CPU & PCI

clocks, down spread -0.5%

Skew from CPU (earlier) to PCI clock (rising edges for

100/33.3MHz)1.5to4ns

Two fixed outputs at 48MHz.

Separate 2.5V and 3.3V supply pins

2.5V or 3.3V output: CPU, IOAPIC

3.3V outputs: PCI, REF, 48MHz

No power supply sequence requirements

Uses external 14.318MHz crystal, no external load cap

required for C_L=18pF crystal

Features include four CPU and eight PCI clocks. Three

reference outputs are available equal to the crystal frequency.

Additionally, the device meets the Pentium power-up

stabilization requirement, assuring that CPU and PCI clocks

are stable within 2ms after power-up.

PD# pin enables low power mode by stopping crystal OSC

and PLL stages. Other power management features include

CPU_STOP#, whichstopsCPU(0:3)clocks, andPCI_STOP#,

which stops PCICLK (0:6) clocks.

High drive CPUCLK outputs typically provide greater than 1

V/ns slew rate into 20pF loads. PCICLK outputs typically

provide better than 1V/ns slew rate into 30pF loads while

maintaining50±5%dutycycle. TheREFclockoutputstypically

provide better than 0.5V/ns slew rates.

48 pin 300 mil SSOP

The ICS9248-55 accepts a 14.318MHz reference crystal or

clock as its input and runs on a 3.3V core supply.

Pin Configuration

Block Diagram

48-Pin SSOP

* Internal Pull-down Resistor of

240K to GND. on indicated inputs

Power Groups

Ground Groups

VDD = Supply for PLL core

VDD1 = REF (0:2), X1, X2

VDD2 = PCICLK_F, PCICLK (0:6)

VDD3 = 48MHz0, 48MHz1

VDDL1 = IOAPIC (0:1)

GND = Ground for PLL core

GND1=REF(0:2),X1,X2

GND2=PCICLK_F,PCICLK(0:6)

GND3=48MHz0,48MHz1

GNDL1=IOAPIC(0:1)

VDDL2 = CPUCLK (0:3)

GNDL2=CPUCLK(0:3)

Pentium is a trademark on Intel Corporation.

ICS reserves the right to make changes in the device data identified in

this publication without further notice. ICS advises its customers to

obtain the latest version of all device data to verify that any

9248-55RevB12/04/98

information being relied upon by the customer is current and accurate.

12 3 4 5 6 7...10

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与ICS9248-55相关器件

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ICS9248-56	ICSI	获取价格	Frequency Timing Generator for Pentium II Systems
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ICS9248-65	ICSI	获取价格	Frequency Timing Generator for PENDIUM II Systems
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ICS9248-73	ICSI	获取价格	Frequency Timing Generator for Pentium II Systems
ICS9248-77	ICSI	获取价格	Frequency Timing Generator for PENTIUM II Systems
ICS9248-78	ICSI	获取价格	Frequency Timing Generator for Pentium II Systems
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