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ICS9248-136 PDF预览

ICS9248-136

更新时间： 2024-11-10 22:11:03
品牌 Logo 应用领域
矽成 - ICSI /
页数 文件大小 规格书
16页 232K
描述
Frequency Generator & Integrated Buffers for K7 Processor

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ICS9248-136 数据手册

 浏览型号ICS9248-136的Datasheet PDF文件第2页浏览型号ICS9248-136的Datasheet PDF文件第3页浏览型号ICS9248-136的Datasheet PDF文件第4页浏览型号ICS9248-136的Datasheet PDF文件第5页浏览型号ICS9248-136的Datasheet PDF文件第6页浏览型号ICS9248-136的Datasheet PDF文件第7页 
ICS9248-136  
Integrated  
Circuit  
Systems, Inc.  
Advance Information  
Frequency Generator & Integrated Buffers for K7 Processor  
Recommended Application:  
Single chip clock solution for SIS 730S K7 chipset.  
Pin Configuration  
VDDA  
(AGPSEL)REF1  
1
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
VDDCPU  
1
*
CPUCLKT0  
CPUCLKC0  
CPUCLKT1  
GND  
VDDSDR  
SDRAM0  
SDRAM1  
SDRAM2  
GND  
SDRAM3  
SDRAM4  
SDRAM5  
VDDSDR  
SDRAM6  
SDRAM7  
GND  
SDRAM8/PD#  
SDRAM9/SDRAM_STOP#  
GND  
SDRAM10/PCI_STOP#  
SDRAM11/CPU_STOP#  
SDRAM12  
VDDSDR  
Output Features:  
1
*(FS3)REF0  
GND  
X1  
X2  
•
1 - Differential pair open drain CPU clock  
•
•
1 - Single-ended open drain CPU clock  
13 - SDRAM @ 3.3V  
VDDPCI  
*(FS1)PCICLK_F  
*(FS2)PCICLK0  
PCICLK1  
PCICLK2  
PCICLK3  
PCICLK4  
GND  
•
•
•
•
6- PCI @3.3V,  
2 - AGP @ 3.3V  
1- 48MHz, @3.3V fixed.  
1- 24/48MHz, @3.3V selectable by I2C  
(Default is 24MHz)  
VDDAGP  
AGPCLK0  
AGPCLK1  
GND  
•
2- REF @3.3V, 14.318MHz.  
GND  
*(FS0)48MHz  
*(MODE)24_48MHz  
VDD48  
Features:  
•
•
•
Up to 166MHz frequency support  
SDATA  
SCLK  
Support FS0-FS3 trapping status bit for I2C read back.  
Support power management: CPU, PCI, SDRAM stop  
and Power down Mode from I2C programming.  
48-Pin 300mil SSOP  
* These inputs have a 120K pull down to GND.  
1 These are double strength.  
•
•
Spread spectrum for EMI control (0 to -0.5%, 0.25%).  
Uses external 14.318MHz crystal  
Skew Specifications:  
•
•
•
•
•
CPU - CPU: < 175ps  
SDRAM - SDRAM < 250ps  
PCI - PCI: < 500ps  
CPU - SDRAM: < 500ps  
CPU (early) - PCI: 1-4ns (typ. 2ns)  
Functionality  
Block Diagram  
AGP  
AGP  
FS3 FS2 FS1 FS0 CPU SDRAM PCICLK  
SEL = 0 SEL = 1  
PLL2  
48MHz  
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
1
100.00 100.00  
100.00 133.33  
100.00 150.00  
100.00 66.67  
33.33  
33.33  
30.00  
33.33  
66.67  
66.67  
60.00  
66.67  
50.00  
50.00  
50.00  
50.00  
24_48MHz  
/ 2  
X1  
X2  
XTAL  
OSC  
REF (1:0)  
2
0
0
0
0
1
1
1
1
1
0
0
0
1
1
0
0
1
0
1
0
112.00 112.00  
125.00 100.00  
124.00 124.00  
133.33 100.00  
133.33 133.33  
33.60  
31.25  
31.00  
33.33  
33.33  
67.20  
62.50  
62.00  
66.67  
66.67  
56.00  
50.00  
46.50  
50.00  
50.00  
PLL1  
Spread  
Spectrum  
CPU  
DIVDER  
Stop  
CPUCLKC0  
CPUCLKT (1:0)  
2
SDRAM  
DIVDER  
Stop  
SDRAM (12:0)  
13  
1
0
0
1
150.00 150.00  
30.00  
60.00  
50.00  
SDATA  
SCLK  
Control  
Logic  
1
1
1
1
1
1
0
0
1
1
1
1
1
1
0
0
1
1
0
1
0
1
0
1
111.11 166.67  
110.00 165.00  
166.67 166.67  
33.33  
33.00  
33.33  
30.00  
32.00  
30.00  
66.67  
66.00  
66.67  
60.00  
64.00  
60.00  
55.56  
55.00  
55.56  
45.00  
48.00  
45.00  
PCI  
DIVDER  
Stop  
PCICLK (4:0)  
PCICLK_F  
AGP (1:0)  
5
2
FS (3:0)  
PD#  
AGP  
DIVDER  
PCI_STOP#  
CPU_STOP#  
SDRAM_STOP#  
MODE  
90.00  
48.00  
45.00  
90.00  
48.00  
60.00  
Config.  
Reg.  
AGP_SEL  
ADVANCE INFORMATION documents contain information on products  
in the formative or design phase development. Characteristic data and  
other specifications are design goals. ICS reserves the right to change or  
discontinue these products without notice.  
9248-136 Rev - 03/29/01  
Third party brands and names are the property of their respective owners.  
1234567...16

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