Datasheet > ICS9248-66

ICS9248-66

更新时间： 2024-09-24 22:55:27

品牌	Logo	应用领域
矽成 - ICSI		/
页数	文件大小	规格书
11页	382K
描述
Frequency Timing Generator for PENTIUM II Systems

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ICS9248-66 数据手册

ICS9248-66

Integrated

Circuit

Advance Information

Systems, Inc.

Frequency Timing Generator for PENTIUM II Systems

Features

Key Specification

Generates the following system clocks:

CPU Output Jitter: <250ps

-3CPUclocks(2.5V, 100/133MHz)

- 8 PCI clocks, including 1 free-running (3.3V, 33MHz)

-1CPU/2clocks(2.5V, 50/66MHz)

-1IOAPICclocks(2.5V,16.67MHz)

-3Fixedfrequency66MHzclocks(3.3V, 66MHz)

-2REFclocks(3.3V,14.318MHz)

CPU/2 Output Jitter. <250ps

IOAPIC Output Jitter: <500ps

48MHz, 3V66, PCIOutputJitter:<500ps

Ref Output Jitter. <1000ps

CPUOutputSkew:<175ps

PCI Output Skew: <500ps

3V66OutputSkew<250ps

CPU to 3V66 Output Offset: 0.0 - 1.5ns (CPU leads)

3V66 to PCI Output Offset: 1.5 - 4.0ns (3V66 leads)

CPU to IOAPIC Output Offset 1.5 - 4.0ns (CPU leads)

-1USBclock(3.3V,48MHz)

Efficient power management through PD#, CPU_STOP#

andPCI_STOP#.

0 to -0.5% typical down spread modulation on CPU,

PCI, IOAPIC, 3V66 and CPU/2 output clocks.

Usesexternal14.318MHzcrystal.

Block Diagram

Pin Configuration

48-pin SSOP

ADVANCE INFORMATION documents contain information on products

in the formative or design phase development. Characteristic data and

other specifications are design goals. ICS reserves the right to change or

discontinue these products without notice.

9248-66 Rev - 7/28/99

12 3 4 5 6 7...11

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