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IBM11M4735C-70J PDF预览

IBM11M4735C-70J

更新时间: 2024-10-28 21:20:51
品牌 Logo 应用领域
国际商业机器公司 - IBM 动态存储器内存集成电路
页数 文件大小 规格书
29页 323K
描述
EDO DRAM Module, 4MX72, 70ns, CMOS, DIMM-168

IBM11M4735C-70J 技术参数

生命周期:Obsolete零件包装代码:DIMM
包装说明:DIMM, DIMM168针数:168
Reach Compliance Code:unknownECCN代码:EAR99
HTS代码:8542.32.00.28风险等级:5.84
Is Samacsys:N访问模式:FAST PAGE WITH EDO
最长访问时间:70 ns其他特性:RAS ONLY/CAS BEFORE RAS/HIDDEN REFRESH
备用内存宽度:36I/O 类型:COMMON
JESD-30 代码:R-XDMA-N168内存密度:301989888 bit
内存集成电路类型:EDO DRAM MODULE内存宽度:72
功能数量:1端口数量:1
端子数量:168字数:4194304 words
字数代码:4000000工作模式:ASYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:4MX72输出特性:3-STATE
封装主体材料:UNSPECIFIED封装代码:DIMM
封装等效代码:DIMM168封装形状:RECTANGULAR
封装形式:MICROELECTRONIC ASSEMBLY电源:5 V
认证状态:Not Qualified刷新周期:4096
自我刷新:NO最大待机电流:0.018 A
子类别:Other Memory ICs最大压摆率:1.17 mA
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:NO
技术:CMOS温度等级:COMMERCIAL
端子形式:NO LEAD端子节距:1.27 mm
端子位置:DUALBase Number Matches:1

IBM11M4735C-70J 数据手册

 浏览型号IBM11M4735C-70J的Datasheet PDF文件第4页浏览型号IBM11M4735C-70J的Datasheet PDF文件第5页浏览型号IBM11M4735C-70J的Datasheet PDF文件第6页浏览型号IBM11M4735C-70J的Datasheet PDF文件第8页浏览型号IBM11M4735C-70J的Datasheet PDF文件第9页浏览型号IBM11M4735C-70J的Datasheet PDF文件第10页 
IBM11M4735C  
IBM11M4735CB  
4M x 72 DRAM MODULE  
AC Characteristics (TA = 0 to +70°C, VCC = 3.3V ± 0.3V or 5.0V ± 0.5V)  
1. VIH (min) and VIL (max) are reference levels for measuring timing of input signals. Transition times are measured between VIH and  
VIL.  
2. An initial pause of 200µs is required after power-up followed by 8 RAS only refresh cycles before proper device operation is  
achieved. In case of using internal refresh counter, a minimum of 8 CAS before RAS refresh cycles instead of 8 RAS only refresh  
cycles is required..  
3. The specified timings include buffer, loading and skew delay adders: 2ns minimum, 5ns maximum delay, no pulse shrinkage to the  
DRAM device timings. The data and RAS signals are not buffered, which preserves the DRAMs access specifications of 60ns and  
70ns.  
4. AC measurements assume tT = 2ns.  
.
Read, Write, Read-Modify-Write and Refresh Cycles (Common Parameters)  
-60  
-70  
Symbol  
Parameter  
Unit  
Notes  
Min  
104  
40  
10  
60  
10  
5
Max  
Min  
124  
50  
10  
70  
12  
5
Max  
tRC  
tRP  
Random Read or Write Cycle Time  
RAS Precharge Time  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
tCP  
CAS Precharge Time  
tRAS  
tCAS  
tASR  
tRAH  
tASC  
RAS Pulse Width  
10K  
10K  
10K  
10K  
CAS Pulse Width  
Row Address Setup Time  
Row Address Hold Time  
Column Address Setup Time  
8
8
2
2
tCAH  
tRCD  
tRAD  
tRSH  
tCSH  
tCRP  
tODD  
tDZO  
tDZC  
tT  
Column Address Hold Time  
RAS to CAS Delay Time  
RAS to Column Address Delay Time  
RAS Hold Time  
10  
12  
10  
15  
48  
10  
20  
-2  
40  
25  
30  
10  
12  
10  
17  
53  
10  
25  
-2  
45  
30  
30  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
1
2
CAS Hold Time  
CAS to RAS Precharge Time  
OE to DIN Delay Time  
3
4
4
OE Delay Time from DIN  
CAS Delay Time from DIN  
Transition Time (Rise and Fall)  
-2  
-2  
2
2
1. Operation within the tRCD(max) limit ensures that tRAC(max) can be met. The tRCD(max) is specified as a reference point only: If tRCD  
is greater than the specified tRCD(max) limit, then access time is controlled by tCAC.  
2. Operation within the tRAD(max) limit ensures that tRAC(max) can be met. The tRAD(max) is specified as a reference point only: If tRAD  
is greater than the specified tRAD(max) limit, then access time is controlled by tAA.  
3. Either tCDD or tODD must be satisfied.  
4. Either tDZC or tDZO must be satisfied.  
©IBM Corporation. All rights reserved.  
Use is further subject to the provisions at the end of this document.  
50H4201  
SA14-4616-02  
Revised 5/96  
Page 7 of 29  
 
 
 
 

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