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IBM11N1645LB-60 PDF预览

IBM11N1645LB-60

更新时间: 2024-11-07 20:33:03
品牌 Logo 应用领域
国际商业机器公司 - IBM 动态存储器光电二极管内存集成电路
页数 文件大小 规格书
31页 344K
描述
EDO DRAM Module, 1MX64, 60ns, CMOS, PDMA168

IBM11N1645LB-60 技术参数

生命周期:ObsoleteReach Compliance Code:unknown
风险等级:5.84最长访问时间:60 ns
I/O 类型:COMMONJESD-30 代码:R-PDMA-N168
内存密度:67108864 bit内存集成电路类型:EDO DRAM MODULE
内存宽度:64端子数量:168
字数:1048576 words字数代码:1000000
最高工作温度:70 °C最低工作温度:
组织:1MX64输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:DIMM
封装等效代码:DIMM168封装形状:RECTANGULAR
封装形式:MICROELECTRONIC ASSEMBLY电源:3.3 V
认证状态:Not Qualified刷新周期:1024
座面最大高度:25.4 mm自我刷新:NO
最大待机电流:0.004 A子类别:DRAMs
最大压摆率:0.66 mA标称供电电压 (Vsup):3.3 V
表面贴装:NO技术:CMOS
温度等级:COMMERCIAL端子形式:NO LEAD
端子节距:1.27 mm端子位置:DUAL
Base Number Matches:1

IBM11N1645LB-60 数据手册

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IBM11N1645L1M  
x 64 E12/12, 3.3V, AuMMDL24DSU-001020633. IBM11N1735Q1M x 72 E12/12, 3.3V, AuMMDL24DSU-001020633.  
IBM11N1645L  
IBM11N1735Q  
1M x 64/72 DRAM Module  
Features  
• 168 Pin JEDEC Standard, Unbuffered 8 Byte  
Dual In-line Memory Module  
• System Performance Benefits:  
-Non buffered for increased performance  
• 1Mx64, 1Mx72 Extended Data Out Page Mode  
DIMMS  
-Reduced noise (35 V /V pins)  
SS CC  
-Byte write, byte read accesses  
-Serial PDs  
• Performance:  
-60  
-6R  
-70  
• Extended Data Out (EDO) Mode, Read-Modify-  
Write Cycles  
tRAC  
tCAC  
tAA  
RAS Access Time  
CAS Access Time  
60ns  
15ns  
60ns 70ns  
17ns 20ns  
30ns 35ns  
• Refresh Modes: RAS-Only, CBR and Hidden  
Refresh  
Access Time From Address 30ns  
tRC  
Cycle Time  
104ns 104ns 124ns  
25ns 25ns 30ns  
• 1024 refresh cycles distributed across 16ms  
• 10/10 addressing (Row/Column)  
tHPC  
EDO Mode Cycle Time  
• All inputs and outputs are LVTTL (3.3V) com-  
patible  
• Card Sizes:  
• Single 3.3V ± 0.3V Power Supply  
-5.25” x 1.0” x 0.102” (TSOP)  
-5.25” x 1.25” x 0.202” (SOJ)  
• Au contacts  
• Optimized for byte-write, non-parity, or ECC  
applications.  
• DRAMS in TSOP OR SOJ Packages  
Description  
IBM11N1645L/IBM11N1735Q industry standard  
168-pin 8-byte Dual In-line Memory Modules  
(DIMMs) which are organized as 1Mx64 and 1Mx72  
high speed memory arrays designed with EDO  
DRAMs for non-parity or ECC applications. The x64  
DIMM uses 4 1Mx16 EDO DRAMs (TSOP or SOJ)  
and the x72 DIMM uses 4 1Mx16 plus 2 1Mx4 EDO  
DRAMs (all in SOJ packages). The use of EDO  
DRAMs allows for a reduction in Page Mode Cycle  
time from 40ns (Fast Page) to 25ns for 60ns DRAM  
modules.  
(SCL) and Data I/O (SDA) lines to synchronously  
clock data between the master (system logic) and  
the slave EEPROM device (DIMM). The EEPROM  
device address pins (SA0-2) are brought out to the  
DIMM tabs to allow 8 unique DIMM/EEPROM  
addresses. The first 128 bytes are utilized by the  
DIMM manufacturer and the second 128 bytes of  
serial PD data are available to the customer.  
All IBM 168-pin DIMMs provide a high performance,  
flexible 8-byte interface in a 5.25” long space-saving  
footprint. Related products include the unbuffered  
X72 ECC DIMMs and the buffered DIMMs (x64, x72  
parity and x72 ECC Optmized) for applications  
which can benefit from the on-card buffers.  
The DIMMs use serial presence detects imple-  
mented via a serial EEPROM using the two pin I C  
2
protocol. This communication protocol uses Clock  
Card Outline (TSOP version shown)  
(Front)  
(Back)  
1
85  
10 11  
94 95  
84  
168  
40 41  
124 125  
©IBM Corporation. All rights reserved.  
Use is further subject to the provisions at the end of this document.  
50H8035  
SA14-4630-02  
Revised 5/96  
Page 1 of 33  

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