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HY64LD16162M-DF85I PDF预览

HY64LD16162M-DF85I

更新时间: 2024-11-11 03:01:59
品牌 Logo 应用领域
海力士 - HYNIX 存储内存集成电路静态存储器
页数 文件大小 规格书
11页 347K
描述
1M x 16 bit Low Low Power 1T/1C Pseudo SRAM

HY64LD16162M-DF85I 技术参数

生命周期:Obsolete零件包装代码:BGA
包装说明:TFBGA, BGA48,6X8,30针数:48
Reach Compliance Code:compliantECCN代码:3A991.B.2.A
HTS代码:8542.32.00.41风险等级:5.84
Is Samacsys:N最长访问时间:85 ns
I/O 类型:COMMONJESD-30 代码:R-PBGA-B48
JESD-609代码:e1长度:8 mm
内存密度:16777216 bit内存集成电路类型:PSEUDO STATIC RAM
内存宽度:16功能数量:1
端子数量:48字数:1048576 words
字数代码:1000000工作模式:ASYNCHRONOUS
最高工作温度:85 °C最低工作温度:-40 °C
组织:1MX16输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:TFBGA
封装等效代码:BGA48,6X8,30封装形状:RECTANGULAR
封装形式:GRID ARRAY, THIN PROFILE, FINE PITCH并行/串行:PARALLEL
电源:2.5 V认证状态:Not Qualified
座面最大高度:1.1 mm最大待机电流:0.000075 A
子类别:Other Memory ICs最大压摆率:0.02 mA
最大供电电压 (Vsup):2.7 V最小供电电压 (Vsup):2.3 V
标称供电电压 (Vsup):2.5 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:TIN SILVER COPPER端子形式:BALL
端子节距:0.75 mm端子位置:BOTTOM
宽度:7 mmBase Number Matches:1

HY64LD16162M-DF85I 数据手册

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HY64LD16162M Series  
Document Title  
1M x 16 bit Low Low Power 1T/1C Pseudo SRAM  
Revision history  
Revision No. History  
Draft Date Remark  
1.0  
1.1  
Initial  
Jan. 04. ’ 01  
Jul. 03. ’ 01  
Preliminary  
Preliminary  
Revised  
- Change Pin Connection  
- Improve tOE from 45ns to 30ns  
- Correct State Diagram  
1.2  
1.3  
Revised  
Jul.18. ’ 01  
Preliminary  
Preliminary  
- Correct Package Dimension  
- Change Absolute Maximum Ratings  
Revised  
Oct. 07. ‘ 01  
• DC Electrical Characteristics ( IDPD,ICC1)  
• State Diagram  
• Power Up Sequence  
• Deep Power Down Sequence  
• Read/Write Cycle Note  
Revised  
1.4  
1.5  
Nov. 14. ’ 01  
Dec. 20. ‘ 01  
Preliminary  
Preliminary  
• DC Electrical Characteristics ( ICC1: 3mA - > 5mA)  
Revised  
• Improve Standby Current ISB1 from 100uA to 80uA  
• Power Up Sequence  
1.6  
Revised  
Feb. 27. ‘ 02  
Preliminary  
- Improve ISB1 80uA to 75uA  
- Improve ICC2 30mA to 20mA  
- Improve Ambient Temperature C/E to E/I  
(0°C~85°C/-25°C~85°C ® -25°C~85°C/-40°C~85°C)  
- Improve Maximum Absolute Ratings  
(Vdd : -0.3V to 3.3V ® -0.3V to 3.6V)  
- Improve tOE 30ns to 20ns  
Revised  
1.7  
Mar. 11. ‘ 02  
Final  
- Pin Description  
- Power Up & Deep Power Down Exit Sequence  
This document is a general product description and is subject to change without notice. Hynix Semiconductor Inc. does not  
assume any responsibility for use of circuits described. No patent licenses are implied.  
Revision 1.7  
March. 2002  
1

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