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HY64UD16162M-DF85C PDF预览

HY64UD16162M-DF85C

更新时间: 2024-11-10 23:57:19
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其他 - ETC /
页数 文件大小 规格书
11页 218K
描述
PSEUDO-STATIC RAM|1MX16|CMOS|BGA|48PIN|PLASTIC

HY64UD16162M-DF85C 数据手册

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HY64UD16162M Series  
Document Title  
1M x 16 bit Low Low Power 1T/1C Pseudo SRAM  
Revision history  
Revision No. History  
Draft Date Remark  
1.0  
1.1  
Initial  
Jan. 04. ’ 01  
Jul. 03. ’ 01  
Preliminary  
Preliminary  
Revised  
- Change Pin Connection  
- Improve tOE from 45ns to 30ns  
- Correct State Diagram  
Revised  
1.2  
1.3  
Jul.18. ’ 01  
Preliminary  
Preliminary  
- Correct Package Dimension  
- Change Absolute Maximum Ratings  
Revised  
Oct. 07. ‘ 01  
• DC Electrical Characteristics ( IDPD,ICC1)  
• State Diagram  
• Power Up Sequence  
• Deep Power Down Sequence  
• Read/Write Cycle Note  
Revised  
1.4  
1.5  
Nov. 14. ’ 01  
Dec. 20. ‘ 01  
Preliminary  
Final  
• DC Electrical Characteristics ( ICC1: 3mA - > 5mA)  
Revised  
• Improve Standby Current ISB1 from 100uA to 80uA  
• Add 70ns Part  
• Power Up Sequence  
This document is a general product description and is subject to change without notice. Hynix Semiconductor Inc. does not  
assume any responsibility for use of circuits described. No patent licenses are implied.  
Revision 1.5  
December. 2001  
1

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