Datasheet > HY64UD16162M-I

HY64UD16162M-I

更新时间： 2024-02-12 01:29:42

品牌	Logo	应用领域
海力士 - HYNIX		静态存储器
页数	文件大小	规格书
11页	350K
描述
1M x 16 bit Low Low Power 1T/1C Pseudo SRAM

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HY64UD16162M-I 数据手册

HY64UD16162M Series

Document Title

1M x 16 bit Low Low Power 1T/1C Pseudo SRAM

Revision history

Revision No. History

Draft Date Remark

1.0

1.1

Initial

Jan. 04. ’ 01

Jul. 03. ’ 01

Preliminary

Revised

- Change Pin Connection

- Improve tOE from 45ns to 30ns

- Correct State Diagram

1.2

1.3

Revised

Jul.18. ’ 01

Preliminary

- Correct Package Dimension

- Change Absolute Maximum Ratings

Revised

Oct. 07. ‘ 01

• DC Electrical Characteristics ( IDPD,ICC1)

• State Diagram

• Power Up Sequence

• Deep Power Down Sequence

• Read/Write Cycle Note

1.4

1.5

Revised

Nov. 14. ’ 01

Dec. 20. ‘ 01

Preliminary

• DC Electrical Characteristics ( ICC1: 3mA - > 5mA)

Revised

• Improve Standby Current ISB1 from 100uA to 80uA

• Add 70ns Part

• Power Up Sequence

1.6

Revised

Feb. 27. ‘ 02

Preliminary

- Improve ISB1@70ns 100uA to 85uA

- Improve ISB1@85ns 80uA to 75uA

- Improve ICC2@70ns 30mA to 25mA

- Improve ICC2@85ns 30mA to 20mA

- Improve Ambient Temperature C/E to E/I

(0°C~85°C/-25°C~85°C ® -25°C~85°C/-40°C~85°C)

- Improve Maximum Absolute Ratings

(Vdd : -0.3V to 3.3V ® -0.3V to 3.6V)

- Improve tOE@85ns 30ns to 20ns

1.7

Revised

Mar. 11. ‘ 02

Final

- Pin Description

- Power Up & Deep Power Down Exit Sequence

This document is a general product description and is subject to change without notice. Hynix Semiconductor Inc. does not

assume any responsibility for use of circuits described. No patent licenses are implied.

Revision 1.7

March. 2002

12 3 4 5 6 7...11

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